Commit 9d0a6fa6 authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Daniel Vetter
Browse files

drm/i915: add render state initialization 



HW guys say that it is not a cool idea to let device
go into rc6 without proper 3d pipeline state.

For each new uninitialized context, generate a
valid null render state to be run on context
creation.

This patch introduces a skeleton with empty states.

v2: - No need to vmap (Chris Wilson)
    - use .c files for state (Daniel Vetter)
    - no need to flush as i915_add_request does it
    - remove parameter for batch alloc size
    - don't wait for the init (Ben Widawsky)

v3: - move to cpu/gpu (Chris Wilson)

Tested-by: Kristen Carlson Accardi <kristen@linux.intel.com> (v1)
Tested-by: default avatarOscar Mateo <oscar.mateo@intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 8b1bc9b4

drivers/gpu/drm/i915/Makefile

+6 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o 
# GEM code

i915-y += i915_cmd_parser.o \

	  i915_gem_context.o \

	  i915_gem_render_state.o \

	  i915_gem_debug.o \

	  i915_gem_dmabuf.o \

	  i915_gem_evict.o \
@@ -32,6 +33,11 @@ i915-y += i915_cmd_parser.o \ 
	  intel_ringbuffer.o \

	  intel_uncore.o



# autogenerated null render state

i915-y += intel_renderstate_gen6.o \

	  intel_renderstate_gen7.o \

	  intel_renderstate_gen8.o



# modesetting core code

i915-y += intel_bios.o \

	  intel_display.o \

drivers/gpu/drm/i915/i915_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -2388,6 +2388,8 @@ int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 
int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,

				   struct drm_file *file);



/* i915_gem_render_state.c */

int i915_gem_render_state_init(struct intel_ring_buffer *ring);

/* i915_gem_evict.c */

int __must_check i915_gem_evict_something(struct drm_device *dev,

					  struct i915_address_space *vm,

drivers/gpu/drm/i915/i915_gem_context.c

+6 −0
Original line number Diff line number Diff line
@@ -699,6 +699,12 @@ static int do_switch(struct intel_ring_buffer *ring, 
		/* obj is kept alive until the next request by its active ref */

		i915_gem_object_ggtt_unpin(from->obj);

		i915_gem_context_unreference(from);

	} else {

		if (to->is_initialized == false) {

			ret = i915_gem_render_state_init(ring);

			if (ret)

				DRM_ERROR("init render state: %d\n", ret);

		}

	}



	to->is_initialized = true;

drivers/gpu/drm/i915/i915_gem_render_state.c

0 → 100644
+194 −0
Original line number Diff line number Diff line 
/*

 * Copyright © 2014 Intel Corporation

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice (including the next

 * paragraph) shall be included in all copies or substantial portions of the

 * Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS

 * IN THE SOFTWARE.

 *

 * Authors:

 *    Mika Kuoppala <mika.kuoppala@intel.com>

 *

 */



#include "i915_drv.h"

#include "intel_renderstate.h"



struct i915_render_state {

	struct drm_i915_gem_object *obj;

	unsigned long ggtt_offset;

	void *batch;

	u32 size;

	u32 len;

};



static struct i915_render_state *render_state_alloc(struct drm_device *dev)

{

	struct i915_render_state *so;

	struct page *page;

	int ret;



	so = kzalloc(sizeof(*so), GFP_KERNEL);

	if (!so)

		return ERR_PTR(-ENOMEM);



	so->obj = i915_gem_alloc_object(dev, 4096);

	if (so->obj == NULL) {

		ret = -ENOMEM;

		goto free;

	}

	so->size = 4096;



	ret = i915_gem_obj_ggtt_pin(so->obj, 4096, 0);

	if (ret)

		goto free_gem;



	BUG_ON(so->obj->pages->nents != 1);

	page = sg_page(so->obj->pages->sgl);



	so->batch = kmap(page);

	if (!so->batch) {

		ret = -ENOMEM;

		goto unpin;

	}



	so->ggtt_offset = i915_gem_obj_ggtt_offset(so->obj);



	return so;

unpin:

	i915_gem_object_ggtt_unpin(so->obj);

free_gem:

	drm_gem_object_unreference(&so->obj->base);

free:

	kfree(so);

	return ERR_PTR(ret);

}



static void render_state_free(struct i915_render_state *so)

{

	kunmap(so->batch);

	i915_gem_object_ggtt_unpin(so->obj);

	drm_gem_object_unreference(&so->obj->base);

	kfree(so);

}



static const struct intel_renderstate_rodata *

render_state_get_rodata(struct drm_device *dev, const int gen)

{

	switch (gen) {

	case 6:

		return &gen6_null_state;

	case 7:

		return &gen7_null_state;

	case 8:

		return &gen8_null_state;

	}



	return NULL;

}



static int render_state_setup(const int gen,

			      const struct intel_renderstate_rodata *rodata,

			      struct i915_render_state *so)

{

	const u64 goffset = i915_gem_obj_ggtt_offset(so->obj);

	u32 reloc_index = 0;

	u32 * const d = so->batch;

	unsigned int i = 0;

	int ret;



	if (!rodata || rodata->batch_items * 4 > so->size)

		return -EINVAL;



	ret = i915_gem_object_set_to_cpu_domain(so->obj, true);

	if (ret)

		return ret;



	while (i < rodata->batch_items) {

		u32 s = rodata->batch[i];



		if (reloc_index < rodata->reloc_items &&

		    i * 4  == rodata->reloc[reloc_index]) {



			s += goffset & 0xffffffff;



			/* We keep batch offsets max 32bit */

			if (gen >= 8) {

				if (i + 1 >= rodata->batch_items ||

				    rodata->batch[i + 1] != 0)

					return -EINVAL;



				d[i] = s;

				i++;

				s = (goffset & 0xffffffff00000000ull) >> 32;

			}



			reloc_index++;

		}



		d[i] = s;

		i++;

	}



	ret = i915_gem_object_set_to_gtt_domain(so->obj, false);

	if (ret)

		return ret;



	if (rodata->reloc_items != reloc_index) {

		DRM_ERROR("not all relocs resolved, %d out of %d\n",

			  reloc_index, rodata->reloc_items);

		return -EINVAL;

	}



	so->len = rodata->batch_items * 4;



	return 0;

}



int i915_gem_render_state_init(struct intel_ring_buffer *ring)

{

	const int gen = INTEL_INFO(ring->dev)->gen;

	struct i915_render_state *so;

	const struct intel_renderstate_rodata *rodata;

	u32 seqno;

	int ret;



	rodata = render_state_get_rodata(ring->dev, gen);

	if (rodata == NULL)

		return 0;



	so = render_state_alloc(ring->dev);

	if (IS_ERR(so))

		return PTR_ERR(so);



	ret = render_state_setup(gen, rodata, so);

	if (ret)

		goto out;



	ret = ring->dispatch_execbuffer(ring,

					i915_gem_obj_ggtt_offset(so->obj),

					so->len,

					I915_DISPATCH_SECURE);

	if (ret)

		goto out;



	ret = i915_add_request(ring, &seqno);



out:

	render_state_free(so);

	return ret;

}

drivers/gpu/drm/i915/intel_renderstate.h

0 → 100644
+48 −0
Original line number Diff line number Diff line 
/*

 * Copyright © 2014 Intel Corporation

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice (including the next

 * paragraph) shall be included in all copies or substantial portions of the

 * Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

 * DEALINGS IN THE SOFTWARE.

 */



#ifndef _INTEL_RENDERSTATE_H

#define _INTEL_RENDERSTATE_H



#include <linux/types.h>



struct intel_renderstate_rodata {

	const u32 *reloc;

	const u32 reloc_items;

	const u32 *batch;

	const u32 batch_items;

};



extern const struct intel_renderstate_rodata gen6_null_state;

extern const struct intel_renderstate_rodata gen7_null_state;

extern const struct intel_renderstate_rodata gen8_null_state;



#define RO_RENDERSTATE(_g)						\

	const struct intel_renderstate_rodata gen ## _g ## _null_state = { \

		.reloc = gen ## _g ## _null_state_relocs,		\

		.reloc_items = sizeof(gen ## _g ## _null_state_relocs)/4, \

		.batch = gen ## _g ## _null_state_batch,		\

		.batch_items = sizeof(gen ## _g ## _null_state_batch)/4, \

	}



#endif /* INTEL_RENDERSTATE_H */

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