Commit 9ca8d1a7 authored by Huazhong Tan's avatar Huazhong Tan Committed by David S. Miller
Browse files

net: hns3: Correct reset event status register 



According to hardware's description, driver should get reset event
from VECTOR0_PF_OTHER_INT_ST(0x20800) instead of
VECTOR0_PF_OTHER_INT_SRC(0x20700).

Signed-off-by: default avatarHuazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: default avatarPeng Li <lipeng321@huawei.com>
Signed-off-by: default avatarSalil Mehta <salil.mehta@huawei.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 9de0b86f

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

+1 −1
Original line number Diff line number Diff line
@@ -2495,7 +2495,7 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 
	u32 cmdq_src_reg;



	/* fetch the events from their corresponding regs */

	rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);

	rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);

	cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);



	/* Assumption: If by any chance reset and mailbox events are reported

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

+1 −0
Original line number Diff line number Diff line
@@ -89,6 +89,7 @@ 


/* Reset related Registers */

#define HCLGE_MISC_RESET_STS_REG	0x20700

#define HCLGE_MISC_VECTOR_INT_STS	0x20800

#define HCLGE_GLOBAL_RESET_REG		0x20A00

#define HCLGE_GLOBAL_RESET_BIT		0x0

#define HCLGE_CORE_RESET_BIT		0x1

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