Commit 9ca03a21 authored by Russell King's avatar Russell King
Browse files

ARM: Factor out common code from cpu_proc_fin() 



All implementations of cpu_proc_fin() start by disabling interrupts
and then flush caches.  Rather than have every processors proc_fin()
implementation do this, move it out into generic code - and move the
cache flush past setup_mm_for_reboot() (so it can benefit from having
caches still enabled.)

This allows cpu_proc_fin() to become independent of the L1/L2 cache
types, and eventually move the L2 cache flushing into the L2 support
code.

Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent b8ab5397

arch/arm/kernel/machine_kexec.c

+5 −1
Original line number Diff line number Diff line
@@ -74,7 +74,11 @@ void machine_kexec(struct kimage *image) 
			   (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE);

	printk(KERN_INFO "Bye!\n");



	cpu_proc_fin();

	local_irq_disable();

	local_fiq_disable();

	setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/

	flush_cache_all();

	cpu_proc_fin();

	flush_cache_all();

	cpu_reset(reboot_code_buffer_phys);

}

arch/arm/kernel/process.c

+13 −4
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 
#include <linux/utsname.h>

#include <linux/uaccess.h>



#include <asm/cacheflush.h>

#include <asm/leds.h>

#include <asm/processor.h>

#include <asm/system.h>
@@ -84,10 +85,9 @@ __setup("hlt", hlt_setup); 


void arm_machine_restart(char mode, const char *cmd)

{

	/*

	 * Clean and disable cache, and turn off interrupts

	 */

	cpu_proc_fin();

	/* Disable interrupts first */

	local_irq_disable();

	local_fiq_disable();



	/*

	 * Tell the mm system that we are going to reboot -
@@ -96,6 +96,15 @@ void arm_machine_restart(char mode, const char *cmd) 
	 */

	setup_mm_for_reboot(mode);



	/* Clean and invalidate caches */

	flush_cache_all();



	/* Turn off caching */

	cpu_proc_fin();



	/* Push out any further dirty data, and ensure cache is empty */

	flush_cache_all();



	/*

	 * Now call the architecture specific reboot code.

	 */

arch/arm/mm/proc-arm1020.S

+1 −5
Original line number Diff line number Diff line
@@ -79,15 +79,11 @@ ENTRY(cpu_arm1020_proc_init) 
 * cpu_arm1020_proc_fin()

 */

ENTRY(cpu_arm1020_proc_fin)

	stmfd	sp!, {lr}

	mov	ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE

	msr	cpsr_c, ip

	bl	arm1020_flush_kern_cache_all

	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register

	bic	r0, r0, #0x1000 		@ ...i............

	bic	r0, r0, #0x000e 		@ ............wca.

	mcr	p15, 0, r0, c1, c0, 0		@ disable caches

	ldmfd	sp!, {pc}

	mov	pc, lr



/*

 * cpu_arm1020_reset(loc)

arch/arm/mm/proc-arm1020e.S

+1 −5
Original line number Diff line number Diff line
@@ -79,15 +79,11 @@ ENTRY(cpu_arm1020e_proc_init) 
 * cpu_arm1020e_proc_fin()

 */

ENTRY(cpu_arm1020e_proc_fin)

	stmfd	sp!, {lr}

	mov	ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE

	msr	cpsr_c, ip

	bl	arm1020e_flush_kern_cache_all

	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register

	bic	r0, r0, #0x1000 		@ ...i............

	bic	r0, r0, #0x000e 		@ ............wca.

	mcr	p15, 0, r0, c1, c0, 0		@ disable caches

	ldmfd	sp!, {pc}

	mov	pc, lr



/*

 * cpu_arm1020e_reset(loc)

arch/arm/mm/proc-arm1022.S

+1 −5
Original line number Diff line number Diff line
@@ -68,15 +68,11 @@ ENTRY(cpu_arm1022_proc_init) 
 * cpu_arm1022_proc_fin()

 */

ENTRY(cpu_arm1022_proc_fin)

	stmfd	sp!, {lr}

	mov	ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE

	msr	cpsr_c, ip

	bl	arm1022_flush_kern_cache_all

	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register

	bic	r0, r0, #0x1000 		@ ...i............

	bic	r0, r0, #0x000e 		@ ............wca.

	mcr	p15, 0, r0, c1, c0, 0		@ disable caches

	ldmfd	sp!, {pc}

	mov	pc, lr



/*

 * cpu_arm1022_reset(loc)

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