Commit 9c9fddd0 authored by Guillaume Thouvenin's avatar Guillaume Thouvenin Committed by Avi Kivity
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KVM: x86 emulator: Add DstAcc operand type 



Add DstAcc operand type. That means that there are 4 bits now for
DstMask.

"In the good old days cpus would have only one register that was able to
 fully participate in arithmetic operations, typically called A for
 Accumulator.  The x86 retains this tradition by having special, shorter
 encodings for the A register (like the cmp opcode), and even some
 instructions that only operate on A (like mul).

 SrcAcc and DstAcc would accommodate these instructions by decoding A
 into the corresponding 'struct operand'."
  -- Avi Kivity

Signed-off-by: default avatarGuillaume Thouvenin <guillaume.thouvenin@ext.bull.net>
Signed-off-by: default avatarAvi Kivity <avi@qumranet.com>
parent defed7ed

arch/x86/kvm/x86_emulate.c

+34 −16
Original line number Diff line number Diff line
@@ -47,25 +47,26 @@ 
#define ImplicitOps (1<<1)	/* Implicit in opcode. No generic decode. */

#define DstReg      (2<<1)	/* Register operand. */

#define DstMem      (3<<1)	/* Memory operand. */

#define DstMask     (3<<1)

#define DstAcc      (4<<1)      /* Destination Accumulator */

#define DstMask     (7<<1)

/* Source operand type. */

#define SrcNone     (0<<3)	/* No source operand. */

#define SrcImplicit (0<<3)	/* Source operand is implicit in the opcode. */

#define SrcReg      (1<<3)	/* Register operand. */

#define SrcMem      (2<<3)	/* Memory operand. */

#define SrcMem16    (3<<3)	/* Memory operand (16-bit). */

#define SrcMem32    (4<<3)	/* Memory operand (32-bit). */

#define SrcImm      (5<<3)	/* Immediate operand. */

#define SrcImmByte  (6<<3)	/* 8-bit sign-extended immediate operand. */

#define SrcMask     (7<<3)

#define SrcNone     (0<<4)	/* No source operand. */

#define SrcImplicit (0<<4)	/* Source operand is implicit in the opcode. */

#define SrcReg      (1<<4)	/* Register operand. */

#define SrcMem      (2<<4)	/* Memory operand. */

#define SrcMem16    (3<<4)	/* Memory operand (16-bit). */

#define SrcMem32    (4<<4)	/* Memory operand (32-bit). */

#define SrcImm      (5<<4)	/* Immediate operand. */

#define SrcImmByte  (6<<4)	/* 8-bit sign-extended immediate operand. */

#define SrcMask     (7<<4)

/* Generic ModRM decode. */

#define ModRM       (1<<6)

#define ModRM       (1<<7)

/* Destination is only written; never read. */

#define Mov         (1<<7)

#define BitOp       (1<<8)

#define MemAbs      (1<<9)      /* Memory operand is absolute displacement */

#define String      (1<<10)     /* String instruction (rep capable) */

#define Stack       (1<<11)     /* Stack instruction (push/pop) */

#define Mov         (1<<8)

#define BitOp       (1<<9)

#define MemAbs      (1<<10)      /* Memory operand is absolute displacement */

#define String      (1<<12)     /* String instruction (rep capable) */

#define Stack       (1<<13)     /* Stack instruction (push/pop) */

#define Group       (1<<14)     /* Bits 3:5 of modrm byte extend opcode */

#define GroupDual   (1<<15)     /* Alternate decoding of mod == 3 */

#define GroupMask   0xff        /* Group number stored in bits 0:7 */
@@ -1060,6 +1061,23 @@ done_prefixes: 
		}

		c->dst.type = OP_MEM;

		break;

	case DstAcc:

		c->dst.type = OP_REG;

		c->dst.bytes = c->op_bytes;

		c->dst.ptr = &c->regs[VCPU_REGS_RAX];

		switch (c->op_bytes) {

			case 1:

				c->dst.val = *(u8 *)c->dst.ptr;

				break;

			case 2:

				c->dst.val = *(u16 *)c->dst.ptr;

				break;

			case 4:

				c->dst.val = *(u32 *)c->dst.ptr;

				break;

		}

		c->dst.orig_val = c->dst.val;

		break;

	}



	if (c->rip_relative)

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