Commit 9c92374b authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

x86/cpu: Move arch_smt_update() to a neutral place 



arch_smt_update() will be used to control IPI/NMI broadcasting via the
shorthand mechanism. Keeping it in the bugs file and calling the apic
function from there is possible, but not really intuitive.

Move it to a neutral place and invoke the bugs function from there.

No functional change.

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Acked-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20190722105219.910317273@linutronix.de
parent 82e57478

arch/x86/include/asm/bugs.h

+2 −0
Original line number Diff line number Diff line
@@ -18,4 +18,6 @@ int ppro_with_ram_bug(void); 
static inline int ppro_with_ram_bug(void) { return 0; }

#endif



extern void cpu_bugs_smt_update(void);



#endif /* _ASM_X86_BUGS_H */

arch/x86/kernel/cpu/bugs.c

+1 −1
Original line number Diff line number Diff line
@@ -700,7 +700,7 @@ static void update_mds_branch_idle(void) 


#define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"



void arch_smt_update(void)

void cpu_bugs_smt_update(void)

{

	/* Enhanced IBRS implies STIBP. No update required. */

	if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)

arch/x86/kernel/cpu/common.c

+9 −0
Original line number Diff line number Diff line
@@ -1945,3 +1945,12 @@ void microcode_check(void) 
	pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");

	pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");

}



/*

 * Invoked from core CPU hotplug code after hotplug operations

 */

void arch_smt_update(void)

{

	/* Handle the speculative execution misfeatures */

	cpu_bugs_smt_update();

}

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