Commit 9c7f85ad authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v4.14-next-dts32-2' of https://github.com/mbgg/linux-mediatek into next/dt 

Pull "Mediatek: 32-bit DTS updates for v4.15" from Matthias Brugger:

- mt7623 update nodes to binding description
- mt2701 add display pwn nodes
- mt2701 update audio node description

* tag 'v4.14-next-dts32-2' of https://github.com/mbgg/linux-mediatek:
  arm: dts: mt7623: remove unused compatible string for pio node
  arm: dts: mt7623: update usb related nodes
  arm: dts: mt7623: update crypto node
  arm: dts: mediatek: update audio node for mt2701 and mt7623
  arm: dts: mt2701: enable display pwm backlight
  arm: dts: mt2701: add pwm backlight device node
parents 2d2cf528 eb54a522

arch/arm/boot/dts/mt2701-evb.dts

+23 −0
Original line number Diff line number Diff line
@@ -56,12 +56,29 @@ 
	bt_sco_codec:bt_sco_codec {

		compatible = "linux,bt-sco";

	};



	backlight_lcd: backlight_lcd {

		compatible = "pwm-backlight";

		pwms = <&bls 0 100000>;

		brightness-levels = <

			  0  16  32  48  64  80  96 112

			128 144 160 176 192 208 224 240

			255

		>;

		default-brightness-level = <9>;

	};

};



&auxadc {

	status = "okay";

};



&bls {

	status = "okay";

	pinctrl-names = "default";

	pinctrl-0 = <&pwm_bls_gpio>;

};



&i2c0 {

	pinctrl-names = "default";

	pinctrl-0 = <&i2c0_pins_a>;
@@ -111,6 +128,12 @@ 
		};

	};



	pwm_bls_gpio: pwm_bls_gpio {

		pins_cmd_dat {

			pinmux = <MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM>;

		};

	};



	spi_pins_a: spi0@0 {

		pins_spi {

			pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,

arch/arm/boot/dts/mt2701.dtsi

+12 −1
Original line number Diff line number Diff line
@@ -430,7 +430,9 @@ 
		compatible = "mediatek,mt2701-audio";

		reg = <0 0x11220000 0 0x2000>,

		      <0 0x112a0000 0 0x20000>;

		interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;

		interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,

			      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;

		interrupt-names	= "afe", "asys";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;



		clocks = <&infracfg CLK_INFRA_AUDIO>,
@@ -530,6 +532,15 @@ 
		#clock-cells = <1>;

	};



	bls: pwm@1400a000 {

		compatible = "mediatek,mt2701-disp-pwm";

		reg = <0 0x1400a000 0 0x1000>;

		#pwm-cells = <2>;

		clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>;

		clock-names = "main", "mm";

		status = "disabled";

	};



	larb0: larb@14010000 {

		compatible = "mediatek,mt2701-smi-larb";

		reg = <0 0x14010000 0 0x1000>;

arch/arm/boot/dts/mt7623.dtsi

+17 −13
Original line number Diff line number Diff line
@@ -227,8 +227,7 @@ 
	};



	pio: pinctrl@10005000 {

		compatible = "mediatek,mt7623-pinctrl",

			     "mediatek,mt2701-pinctrl";

		compatible = "mediatek,mt7623-pinctrl";

		reg = <0 0x1000b000 0 0x1000>;

		mediatek,pctl-regmap = <&syscfg_pctl_a>;

		pins-are-numbered;
@@ -544,7 +543,9 @@ 
			     "mediatek,mt2701-audio";

		reg = <0 0x11220000 0 0x2000>,

		      <0 0x112a0000 0 0x20000>;

		interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;

		interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,

			      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;

		interrupt-names	= "afe", "asys";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;



		clocks = <&infracfg CLK_INFRA_AUDIO>,
@@ -678,7 +679,7 @@ 
		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&hifsys CLK_HIFSYS_USB0PHY>,

			 <&topckgen CLK_TOP_ETHIF_SEL>;

		clock-names = "sys_ck", "free_ck";

		clock-names = "sys_ck", "ref_ck";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;

		phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;

		status = "disabled";
@@ -688,8 +689,6 @@ 
		compatible = "mediatek,mt7623-u3phy",

			     "mediatek,mt2701-u3phy";

		reg = <0 0x1a1c4000 0 0x0700>;

		clocks = <&clk26m>;

		clock-names = "u3phya_ref";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;
@@ -697,12 +696,16 @@ 


		u2port0: usb-phy@1a1c4800 {

			reg = <0 0x1a1c4800 0 0x0100>;

			clocks = <&topckgen CLK_TOP_USB_PHY48M>;

			clock-names = "ref";

			#phy-cells = <1>;

			status = "okay";

		};



		u3port0: usb-phy@1a1c4900 {

			reg = <0 0x1a1c4900 0 0x0700>;

			clocks = <&clk26m>;

			clock-names = "ref";

			#phy-cells = <1>;

			status = "okay";

		};
@@ -717,7 +720,7 @@ 
		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&hifsys CLK_HIFSYS_USB1PHY>,

			 <&topckgen CLK_TOP_ETHIF_SEL>;

		clock-names = "sys_ck", "free_ck";

		clock-names = "sys_ck", "ref_ck";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;

		phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;

		status = "disabled";
@@ -727,8 +730,6 @@ 
		compatible = "mediatek,mt7623-u3phy",

			     "mediatek,mt2701-u3phy";

		reg = <0 0x1a244000 0 0x0700>;

		clocks = <&clk26m>;

		clock-names = "u3phya_ref";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;
@@ -736,12 +737,16 @@ 


		u2port1: usb-phy@1a244800 {

			reg = <0 0x1a244800 0 0x0100>;

			clocks = <&topckgen CLK_TOP_USB_PHY48M>;

			clock-names = "ref";

			#phy-cells = <1>;

			status = "okay";

		};



		u3port1: usb-phy@1a244900 {

			reg = <0 0x1a244900 0 0x0700>;

			clocks = <&clk26m>;

			clock-names = "ref";

			#phy-cells = <1>;

			status = "okay";

		};
@@ -782,16 +787,15 @@ 
	};



	crypto: crypto@1b240000 {

		compatible = "mediatek,mt7623-crypto";

		compatible = "mediatek,eip97-crypto";

		reg = <0 0x1b240000 0 0x20000>;

		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,

			 <&ethsys CLK_ETHSYS_CRYPTO>;

		clock-names = "ethif","cryp";

		clocks = <&ethsys CLK_ETHSYS_CRYPTO>;

		clock-names = "cryp";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;

		status = "disabled";

	};

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