Commit 9c7ae8ed authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'hisi-arm64-dt-for-5.8' of git://github.com/hisilicon/linux-hisi into arm/dt 

ARM64: DT: Hisilicon SoCs DT updates for 5.8

- Add pinconf for spi2 and spi3 nodes and increase the drive
  strength to achieve the max speed for the Hikey960 board
- Add CTI nodes for the Hikey620 board

* tag 'hisi-arm64-dt-for-5.8' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hi6220: Add CTI options
  arm64: dts: hikey960: pinctrl: Fix spi2/spi3 pinconf

Link: https://lore.kernel.org/r/5EBE430E.6090508@hisilicon.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 8c915019 fd955a7e

arch/arm64/boot/dts/hisilicon/hi3660.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -974,7 +974,7 @@ 
			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;

			clock-names = "apb_pclk";

			pinctrl-names = "default";

			pinctrl-0 = <&spi2_pmx_func>;

			pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>;

			num-cs = <1>;

			cs-gpios = <&gpio27 2 0>;

			status = "disabled";
@@ -989,7 +989,7 @@ 
			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;

			clock-names = "apb_pclk";

			pinctrl-names = "default";

			pinctrl-0 = <&spi3_pmx_func>;

			pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>;

			num-cs = <1>;

			cs-gpios = <&gpio18 5 0>;

			status = "disabled";

arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi

+122 −8
Original line number Diff line number Diff line
@@ -213,7 +213,7 @@ 
			};

		};



		etm@f659c000 {

		etm0: etm@f659c000 {

			compatible = "arm,coresight-etm4x", "arm,primecell";

			reg = <0 0xf659c000 0 0x1000>;
@@ -232,7 +232,7 @@ 
			};

		};



		etm@f659d000 {

		etm1: etm@f659d000 {

			compatible = "arm,coresight-etm4x", "arm,primecell";

			reg = <0 0xf659d000 0 0x1000>;
@@ -251,7 +251,7 @@ 
			};

		};



		etm@f659e000 {

		etm2: etm@f659e000 {

			compatible = "arm,coresight-etm4x", "arm,primecell";

			reg = <0 0xf659e000 0 0x1000>;
@@ -270,7 +270,7 @@ 
			};

		};



		etm@f659f000 {

		etm3: etm@f659f000 {

			compatible = "arm,coresight-etm4x", "arm,primecell";

			reg = <0 0xf659f000 0 0x1000>;
@@ -289,7 +289,7 @@ 
			};

		};



		etm@f65dc000 {

		etm4: etm@f65dc000 {

			compatible = "arm,coresight-etm4x", "arm,primecell";

			reg = <0 0xf65dc000 0 0x1000>;
@@ -308,7 +308,7 @@ 
			};

		};



		etm@f65dd000 {

		etm5: etm@f65dd000 {

			compatible = "arm,coresight-etm4x", "arm,primecell";

			reg = <0 0xf65dd000 0 0x1000>;
@@ -327,7 +327,7 @@ 
			};

		};



		etm@f65de000 {

		etm6: etm@f65de000 {

			compatible = "arm,coresight-etm4x", "arm,primecell";

			reg = <0 0xf65de000 0 0x1000>;
@@ -346,7 +346,7 @@ 
			};

		};



		etm@f65df000 {

		etm7: etm@f65df000 {

			compatible = "arm,coresight-etm4x", "arm,primecell";

			reg = <0 0xf65df000 0 0x1000>;
@@ -364,5 +364,119 @@ 
				};

			};

		};



		/* System CTIs */

		/* CTI 0 - TMC and TPIU connections */

		cti@f6403000 {

			compatible = "arm,coresight-cti", "arm,primecell";

			reg = <0 0xf6403000 0 0x1000>;



			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;

			clock-names = "apb_pclk";

		};



		/* CTI - CPU-0 */

		cti@f6598000 {

			compatible = "arm,coresight-cti-v8-arch",

				     "arm,coresight-cti", "arm,primecell";

			reg = <0 0xf6598000 0 0x1000>;



			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;

			clock-names = "apb_pclk";



			cpu = <&cpu0>;

			arm,cs-dev-assoc = <&etm0>;

		};



		/* CTI - CPU-1 */

		cti@f6599000 {

			compatible = "arm,coresight-cti-v8-arch",

				     "arm,coresight-cti", "arm,primecell";

			reg = <0 0xf6599000 0 0x1000>;



			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;

			clock-names = "apb_pclk";



			cpu = <&cpu1>;

			arm,cs-dev-assoc = <&etm1>;

		};



		/* CTI - CPU-2 */

		cti@f659a000 {

			compatible = "arm,coresight-cti-v8-arch",

				     "arm,coresight-cti", "arm,primecell";

			reg = <0 0xf659a000 0 0x1000>;



			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;

			clock-names = "apb_pclk";



			cpu = <&cpu2>;

			arm,cs-dev-assoc = <&etm2>;

		};



		/* CTI - CPU-3 */

		cti@f659b000 {

			compatible = "arm,coresight-cti-v8-arch",

				     "arm,coresight-cti", "arm,primecell";

			reg = <0 0xf659b000 0 0x1000>;



			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;

			clock-names = "apb_pclk";



			cpu = <&cpu3>;

			arm,cs-dev-assoc = <&etm3>;

		};



		/* CTI - CPU-4 */

		cti@f65d8000 {

			compatible = "arm,coresight-cti-v8-arch",

				     "arm,coresight-cti", "arm,primecell";

			reg = <0 0xf65d8000 0 0x1000>;



			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;

			clock-names = "apb_pclk";



			cpu = <&cpu4>;

			arm,cs-dev-assoc = <&etm4>;

		};



		/* CTI - CPU-5 */

		cti@f65d9000 {

			compatible = "arm,coresight-cti-v8-arch",

				     "arm,coresight-cti", "arm,primecell";

			reg = <0 0xf65d9000 0 0x1000>;



			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;

			clock-names = "apb_pclk";



			cpu = <&cpu5>;

			arm,cs-dev-assoc = <&etm5>;

		};



		/* CTI - CPU-6 */

		cti@f65da000 {

			compatible = "arm,coresight-cti-v8-arch",

				     "arm,coresight-cti", "arm,primecell";

			reg = <0 0xf65da000 0 0x1000>;



			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;

			clock-names = "apb_pclk";



			cpu = <&cpu6>;

			arm,cs-dev-assoc = <&etm6>;

		};



		/* CTI - CPU-7 */

		cti@f65db000 {

			compatible = "arm,coresight-cti-v8-arch",

				     "arm,coresight-cti", "arm,primecell";

			reg = <0 0xf65db000 0 0x1000>;



			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;

			clock-names = "apb_pclk";



			cpu = <&cpu7>;

			arm,cs-dev-assoc = <&etm7>;

		};

	};

};

arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -717,7 +717,7 @@ 
			spi3_cfg_func: spi3_cfg_func {

				pinctrl-single,pins = <

					0x008 0x0 /* SPI3_CLK */

					0x0 /* SPI3_DI */

					0x00c 0x0 /* SPI3_DI */

					0x010 0x0 /* SPI3_DO */

					0x014 0x0 /* SPI3_CS0_N */

				>;
@@ -734,7 +734,7 @@ 
					PULL_UP

				>;

				pinctrl-single,drive-strength = <

					DRIVE7_02MA DRIVE6_MASK

					DRIVE7_06MA DRIVE6_MASK

				>;

			};

		};
@@ -1031,7 +1031,7 @@ 
					PULL_UP

				>;

				pinctrl-single,drive-strength = <

					DRIVE7_02MA DRIVE6_MASK

					DRIVE7_06MA DRIVE6_MASK

				>;

			};

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