Commit 9c44bf4c authored by Tomislav Požega's avatar Tomislav Požega Committed by Kalle Valo
Browse files

ath10k: use ath10k_pci_soc_ functions for all warm_reset instances 



Use ath10k_pci_soc_read32 / ath10k_pci_soc_write32 functions for
the rest of warm_reset functions. Until now these have been used
only for ath10k_pci_warm_reset_si0, but since they already exist
it makes sense to simplify code a bit.
Runtime tested with QCA9862.

Signed-off-by: default avatarTomislav Požega <pozega.tomislav@gmail.com>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent 7921ae09

drivers/net/wireless/ath/ath10k/pci.c

+11 −15
Original line number Diff line number Diff line
@@ -2567,9 +2567,8 @@ static void ath10k_pci_warm_reset_cpu(struct ath10k *ar) 


	ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);



	val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +

				SOC_RESET_CONTROL_ADDRESS);

	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,

	val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);

	ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,

			       val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);

}
@@ -2577,13 +2576,12 @@ static void ath10k_pci_warm_reset_ce(struct ath10k *ar) 
{

	u32 val;



	val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +

				SOC_RESET_CONTROL_ADDRESS);

	val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);



	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,

	ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,

			       val | SOC_RESET_CONTROL_CE_RST_MASK);

	msleep(10);

	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,

	ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,

			       val & ~SOC_RESET_CONTROL_CE_RST_MASK);

}
@@ -2591,10 +2589,8 @@ static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar) 
{

	u32 val;



	val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +

				SOC_LF_TIMER_CONTROL0_ADDRESS);

	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +

			   SOC_LF_TIMER_CONTROL0_ADDRESS,

	val = ath10k_pci_soc_read32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS);

	ath10k_pci_soc_write32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS,

			       val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);

}

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