Commit 9c3f2b54 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: rename amdgpu_program_register_sequence 



add device for consistency with other functions in this file.

Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 131b4b36

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −1
Original line number Diff line number Diff line
@@ -1913,7 +1913,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 
void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);

int amdgpu_ttm_init(struct amdgpu_device *adev);

void amdgpu_ttm_fini(struct amdgpu_device *adev);

void amdgpu_program_register_sequence(struct amdgpu_device *adev,

void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,

					     const u32 *registers,

					     const u32 array_size);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+4 −4
Original line number Diff line number Diff line
@@ -342,7 +342,7 @@ static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) 
}



/**

 * amdgpu_program_register_sequence - program an array of registers.

 * amdgpu_device_program_register_sequence - program an array of registers.

 *

 * @adev: amdgpu_device pointer

 * @registers: pointer to the register array
@@ -351,7 +351,7 @@ static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) 
 * Programs an array or registers with and and or masks.

 * This is a helper for setting golden registers.

 */

void amdgpu_program_register_sequence(struct amdgpu_device *adev,

void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,

					     const u32 *registers,

					     const u32 array_size)

{

drivers/gpu/drm/amd/amdgpu/cik.c

+60 −60
Original line number Diff line number Diff line
@@ -755,72 +755,72 @@ static void cik_init_golden_registers(struct amdgpu_device *adev) 


	switch (adev->asic_type) {

	case CHIP_BONAIRE:

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							bonaire_mgcg_cgcg_init,

							ARRAY_SIZE(bonaire_mgcg_cgcg_init));

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							bonaire_golden_registers,

							ARRAY_SIZE(bonaire_golden_registers));

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							bonaire_golden_common_registers,

							ARRAY_SIZE(bonaire_golden_common_registers));

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							bonaire_golden_spm_registers,

							ARRAY_SIZE(bonaire_golden_spm_registers));

		break;

	case CHIP_KABINI:

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							kalindi_mgcg_cgcg_init,

							ARRAY_SIZE(kalindi_mgcg_cgcg_init));

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							kalindi_golden_registers,

							ARRAY_SIZE(kalindi_golden_registers));

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							kalindi_golden_common_registers,

							ARRAY_SIZE(kalindi_golden_common_registers));

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							kalindi_golden_spm_registers,

							ARRAY_SIZE(kalindi_golden_spm_registers));

		break;

	case CHIP_MULLINS:

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							kalindi_mgcg_cgcg_init,

							ARRAY_SIZE(kalindi_mgcg_cgcg_init));

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							godavari_golden_registers,

							ARRAY_SIZE(godavari_golden_registers));

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							kalindi_golden_common_registers,

							ARRAY_SIZE(kalindi_golden_common_registers));

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							kalindi_golden_spm_registers,

							ARRAY_SIZE(kalindi_golden_spm_registers));

		break;

	case CHIP_KAVERI:

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							spectre_mgcg_cgcg_init,

							ARRAY_SIZE(spectre_mgcg_cgcg_init));

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							spectre_golden_registers,

							ARRAY_SIZE(spectre_golden_registers));

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							spectre_golden_common_registers,

							ARRAY_SIZE(spectre_golden_common_registers));

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							spectre_golden_spm_registers,

							ARRAY_SIZE(spectre_golden_spm_registers));

		break;

	case CHIP_HAWAII:

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							hawaii_mgcg_cgcg_init,

							ARRAY_SIZE(hawaii_mgcg_cgcg_init));

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							hawaii_golden_registers,

							ARRAY_SIZE(hawaii_golden_registers));

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							hawaii_golden_common_registers,

							ARRAY_SIZE(hawaii_golden_common_registers));

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							hawaii_golden_spm_registers,

							ARRAY_SIZE(hawaii_golden_spm_registers));

		break;

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

+12 −12
Original line number Diff line number Diff line
@@ -145,18 +145,18 @@ static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev) 
{

	switch (adev->asic_type) {

	case CHIP_FIJI:

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							fiji_mgcg_cgcg_init,

							ARRAY_SIZE(fiji_mgcg_cgcg_init));

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							golden_settings_fiji_a10,

							ARRAY_SIZE(golden_settings_fiji_a10));

		break;

	case CHIP_TONGA:

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							tonga_mgcg_cgcg_init,

							ARRAY_SIZE(tonga_mgcg_cgcg_init));

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							golden_settings_tonga_a11,

							ARRAY_SIZE(golden_settings_tonga_a11));

		break;

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

+15 −15
Original line number Diff line number Diff line
@@ -154,26 +154,26 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) 
{

	switch (adev->asic_type) {

	case CHIP_CARRIZO:

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							cz_mgcg_cgcg_init,

							ARRAY_SIZE(cz_mgcg_cgcg_init));

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							cz_golden_settings_a11,

							ARRAY_SIZE(cz_golden_settings_a11));

		break;

	case CHIP_STONEY:

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							stoney_golden_settings_a11,

							ARRAY_SIZE(stoney_golden_settings_a11));

		break;

	case CHIP_POLARIS11:

	case CHIP_POLARIS12:

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							polaris11_golden_settings_a11,

							ARRAY_SIZE(polaris11_golden_settings_a11));

		break;

	case CHIP_POLARIS10:

		amdgpu_program_register_sequence(adev,

		amdgpu_device_program_register_sequence(adev,

							polaris10_golden_settings_a11,

							ARRAY_SIZE(polaris10_golden_settings_a11));

		break;

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