Commit 9bad40a2 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915/selftests: Always flush before unpining after writing 



Be consistent, and even when we know we had used a WC, flush the mapped
object after writing into it. The flush understands the mapping type and
will only clflush if !I915_MAP_WC, but will always insert a wmb [sfence]
so that we can be sure that all writes are visible.

v2: Add the unconditional wmb so we are know that we always flush the
writes to memory/HW at that point.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200511141304.599-1-chris@chris-wilson.co.uk
parent b0a997ae

drivers/gpu/drm/i915/gem/i915_gem_object_blt.c

+6 −2
Original line number Diff line number Diff line
@@ -78,10 +78,12 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce, 
	} while (rem);



	*cmd = MI_BATCH_BUFFER_END;

	intel_gt_chipset_flush(ce->vm->gt);



	i915_gem_object_flush_map(pool->obj);

	i915_gem_object_unpin_map(pool->obj);



	intel_gt_chipset_flush(ce->vm->gt);



	batch = i915_vma_instance(pool->obj, ce->vm, NULL);

	if (IS_ERR(batch)) {

		err = PTR_ERR(batch);
@@ -289,10 +291,12 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce, 
	} while (rem);



	*cmd = MI_BATCH_BUFFER_END;

	intel_gt_chipset_flush(ce->vm->gt);



	i915_gem_object_flush_map(pool->obj);

	i915_gem_object_unpin_map(pool->obj);



	intel_gt_chipset_flush(ce->vm->gt);



	batch = i915_vma_instance(pool->obj, ce->vm, NULL);

	if (IS_ERR(batch)) {

		err = PTR_ERR(batch);

drivers/gpu/drm/i915/gem/i915_gem_pages.c

+1 −0
Original line number Diff line number Diff line
@@ -391,6 +391,7 @@ void __i915_gem_object_flush_map(struct drm_i915_gem_object *obj, 
	GEM_BUG_ON(range_overflows_t(typeof(obj->base.size),

				     offset, size, obj->base.size));



	wmb(); /* let all previous writes be visible to coherent partners */

	obj->mm.dirty = true;



	if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE)

drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c

+2 −0
Original line number Diff line number Diff line
@@ -158,6 +158,8 @@ static int wc_set(struct context *ctx, unsigned long offset, u32 v) 
		return PTR_ERR(map);



	map[offset / sizeof(*map)] = v;



	__i915_gem_object_flush_map(ctx->obj, offset, sizeof(*map));

	i915_gem_object_unpin_map(ctx->obj);



	return 0;

drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c

+1 −0
Original line number Diff line number Diff line
@@ -84,6 +84,7 @@ igt_emit_store_dw(struct i915_vma *vma, 
	}

	*cmd = MI_BATCH_BUFFER_END;



	i915_gem_object_flush_map(obj);

	i915_gem_object_unpin_map(obj);



	intel_gt_chipset_flush(vma->vm->gt);

drivers/gpu/drm/i915/gt/selftest_ring_submission.c

+2 −0
Original line number Diff line number Diff line
@@ -54,6 +54,8 @@ static struct i915_vma *create_wally(struct intel_engine_cs *engine) 
	*cs++ = STACK_MAGIC;



	*cs++ = MI_BATCH_BUFFER_END;



	i915_gem_object_flush_map(obj);

	i915_gem_object_unpin_map(obj);



	vma->private = intel_context_create(engine); /* dummy residuals */

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