Commit 9ba64fe3 authored by Shawn Guo's avatar Shawn Guo
Browse files

ARM: imx: enable suspend for imx6sl 



The imx6sl low power mode implementation inherits imx6q/dl one,
and pm-imx6q.c can just work for imx6sl with some minor updates.
Let's enable imx6sl suspend support by reusing pm-imx6q.c and use
cpu_is_imxXX() to handle the those minor differences between imx6sl
and imx6q/dl.

Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent d48866fe

arch/arm/mach-imx/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -102,6 +102,8 @@ obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o 


ifeq ($(CONFIG_PM),y)

obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o

# i.MX6SL reuses pm-imx6q.c

obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o

endif



# i.MX5 based machines

arch/arm/mach-imx/clk-imx6sl.c

+3 −0
Original line number Diff line number Diff line
@@ -127,6 +127,9 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) 
	base = of_iomap(np, 0);

	WARN_ON(!base);



	/* Reuse imx6q pm code */

	imx6q_pm_set_ccm_base(base);



	/*                                              name                reg       shift width parent_names     num_parents */

	clks[IMX6SL_CLK_STEP]             = imx_clk_mux("step",             base + 0xc,  8,  1, step_sels,         ARRAY_SIZE(step_sels));

	clks[IMX6SL_CLK_PLL1_SW]          = imx_clk_mux("pll1_sw",          base + 0xc,  2,  1, pll1_sw_sels,      ARRAY_SIZE(pll1_sw_sels));

arch/arm/mach-imx/mach-imx6sl.c

+3 −0
Original line number Diff line number Diff line
@@ -47,6 +47,9 @@ static void __init imx6sl_init_machine(void) 
	of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);



	imx6sl_fec_init();

	imx_anatop_init();

	/* Reuse imx6q pm code */

	imx6q_pm_init();

}



static void __init imx6sl_init_irq(void)

arch/arm/mach-imx/mxc.h

+5 −0
Original line number Diff line number Diff line
@@ -153,6 +153,11 @@ extern unsigned int __mxc_cpu_type; 
#endif



#ifndef __ASSEMBLY__

static inline bool cpu_is_imx6sl(void)

{

	return __mxc_cpu_type == MXC_CPU_IMX6SL;

}



static inline bool cpu_is_imx6dl(void)

{

	return __mxc_cpu_type == MXC_CPU_IMX6DL;

arch/arm/mach-imx/pm-imx6q.c

+8 −1
Original line number Diff line number Diff line
@@ -144,6 +144,12 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) 
		val |= 0x3 << BP_CLPCR_STBY_COUNT;

		val |= BM_CLPCR_VSTBY;

		val |= BM_CLPCR_SBYOS;

		if (cpu_is_imx6sl()) {

			val |= BM_CLPCR_BYPASS_PMIC_READY;

			val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;

		} else {

			val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;

		}

		break;

	default:

		return -EINVAL;
@@ -181,6 +187,7 @@ static int imx6q_pm_enter(suspend_state_t state) 
		imx_set_cpu_jump(0, v7_cpu_resume);

		/* Zzz ... */

		cpu_suspend(0, imx6q_suspend_finish);

		if (cpu_is_imx6q() || cpu_is_imx6dl())

			imx_smp_prepare();

		imx_anatop_post_resume();

		imx_gpc_post_resume();

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