Commit 9ba5a8a5 authored by Grygorii Strashko's avatar Grygorii Strashko Committed by David S. Miller
Browse files

arm64: dts: k3-am654-base-board: add mcu cpsw nuss pinmux and phy defs 



AM654 EVM base board has TI DP83867 PHY connected to external CPSW NUSS
Port 1 in rgmii-rxid mode.

Hence, add pinmux and Ethernet PHY configuration for TI am654 SoC Gigabit
Ethernet two ports Switch subsystem (CPSW NUSS).

Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
Tested-by: default avatarMurali Karicheri <m-karicheri2@ti.com>
Tested-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ba86a6e9

arch/arm64/boot/dts/ti/k3-am654-base-board.dts

+42 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 


#include "k3-am654.dtsi"

#include <dt-bindings/input/input.h>

#include <dt-bindings/net/ti-dp83867.h>



/ {

	compatible =  "ti,am654-evm", "ti,am654";
@@ -95,7 +96,30 @@ 
	wkup_pca554_default: wkup_pca554_default {

		pinctrl-single,pins = <

			AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */

		>;

	};



	mcu_cpsw_pins_default: mcu_cpsw_pins_default {

		pinctrl-single,pins = <

			AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */

			AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */

			AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */

			AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */

			AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */

			AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */

			AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */

			AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */

			AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */

			AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */

			AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */

			AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */

		>;

	};



	mcu_mdio_pins_default: mcu_mdio1_pins_default {

		pinctrl-single,pins = <

			AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */

			AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */

		>;

	};

};
@@ -419,3 +443,21 @@ 
		data-lanes = <1 2>;

	};

};



&mcu_cpsw {

	pinctrl-names = "default";

	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;

};



&davinci_mdio {

	phy0: ethernet-phy@0 {

		reg = <0>;

		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;

		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

	};

};



&cpsw_port1 {

	phy-mode = "rgmii-rxid";

	phy-handle = <&phy0>;

};

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