memory: tegra: Add EMC scaling sequence code for Tegra210

obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o tegra186-emc.o

obj-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o tegra186-emc.o

tegra210-emc-y := tegra210-emc-core.o

tegra210-emc-y := tegra210-emc-core.o tegra210-emc-cc-r21021.o

		(((value) & 0xffff0000) | ((value) & 0xffff) * (speedup))

static const struct tegra210_emc_sequence *tegra210_emc_sequences[] = {

	&tegra210_emc_r21021,

};

static const struct tegra210_emc_table_register_offsets

#define EMC_INTSTATUS_CLKCHANGE_COMPLETE			BIT(4)

#define EMC_DBG							0x8

#define EMC_DBG_WRITE_MUX_ACTIVE				BIT(1)

#define EMC_DBG_WRITE_ACTIVE_ONLY				BIT(30)

#define EMC_CFG							0xc

#define EMC_CFG_DRAM_CLKSTOP_PD					BIT(31)

#define EMC_CFG_DRAM_CLKSTOP_SR					BIT(30)

#define EMC_CFG_DRAM_ACPD					BIT(29)

#define EMC_CFG_DYN_SELF_REF					BIT(28)

#define EMC_PIN							0x24

#define EMC_PIN_PIN_CKE						BIT(0)

#define EMC_PIN_PIN_CKEB					BIT(1)

#define EMC_PIN_PIN_CKE_PER_DEV					BIT(2)

#define EMC_TIMING_CONTROL					0x28

#define EMC_RC							0x2c

#define EMC_RFC							0x30

#define EMC_WEXT						0xb8

#define EMC_RFC_SLR						0xc0

#define EMC_MRS_WAIT_CNT2					0xc4

#define EMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_SHIFT		16

#define EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_SHIFT		0

#define EMC_MRS_WAIT_CNT					0xc8

#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT			0

#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK			\

#define EMC_PDEX2CKE						0x118

#define EMC_CKE2PDEN						0x11c

#define EMC_MPC							0x128

#define EMC_EMRS2						0x12c

#define EMC_EMRS2_USE_EMRS2_LONG_CNT				BIT(26)

#define EMC_MRW2						0x134

#define EMC_MRW3						0x138

#define EMC_MRW4						0x13c

#define EMC_R2R							0x144

#define EMC_EINPUT						0x14c

#define EMC_EINPUT_DURATION					0x150

#define EMC_PUTERM_EXTRA					0x154

#define EMC_TCKESR						0x158

#define EMC_TPD							0x15c

#define EMC_AUTO_CAL_CONFIG					0x2a4

#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_COMPUTE_START		BIT(0)

#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_MEASURE_STALL		BIT(9)

#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_UPDATE_STALL		BIT(10)

#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE			BIT(29)

#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START			BIT(31)

#define EMC_EMC_STATUS						0x2b4

#define EMC_EMC_STATUS_MRR_DIVLD				BIT(20)

#define EMC_EMC_STATUS_TIMING_UPDATE_STALLED			BIT(23)

#define EMC_EMC_STATUS_DRAM_IN_POWERDOWN_SHIFT			4

#define EMC_EMC_STATUS_DRAM_IN_POWERDOWN_MASK			\

	(0x3 << EMC_EMC_STATUS_DRAM_IN_POWERDOWN_SHIFT)

#define EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_SHIFT		8

#define EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_MASK		\

	(0x3 << EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_SHIFT)

#define EMC_CFG_2						0x2b8

#define EMC_CFG_DIG_DLL						0x2bc

#define EMC_CFG_DIG_DLL_CFG_DLL_EN				BIT(0)

#define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_UNTIL_LOCK		BIT(1)

#define EMC_WDV_MASK						0x2d0

#define EMC_RDV_EARLY_MASK					0x2d4

#define EMC_RDV_EARLY						0x2d8

#define EMC_AUTO_CAL_CONFIG8					0x2dc

#define EMC_ZCAL_INTERVAL					0x2e0

#define EMC_ZCAL_WAIT_CNT					0x2e4

#define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_MASK			0x7ff

#define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_SHIFT			0

#define EMC_ZQ_CAL						0x2ec

#define EMC_ZQ_CAL_DEV_SEL_SHIFT				30

#define EMC_ZQ_CAL_LONG						BIT(4)

#define EMC_ZQ_CAL_ZQ_LATCH_CMD					BIT(1)

#define EMC_ZQ_CAL_ZQ_CAL_CMD					BIT(0)

#define EMC_FDPD_CTRL_DQ					0x310

#define EMC_FDPD_CTRL_CMD					0x314

#define EMC_PMACRO_CMD_BRICK_CTRL_FDPD				0x318

#define EMC_TR_TIMING_0						0x3b4

#define EMC_TR_CTRL_1						0x3bc

#define EMC_TR_RDV						0x3c4

#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE			0x3cc

#define EMC_SEL_DPD_CTRL					0x3d8

#define EMC_SEL_DPD_CTRL_DATA_SEL_DPD_EN			BIT(8)

#define EMC_SEL_DPD_CTRL_ODT_SEL_DPD_EN				BIT(5)

#define EMC_SEL_DPD_CTRL_RESET_SEL_DPD_EN			BIT(4)

#define EMC_SEL_DPD_CTRL_CA_SEL_DPD_EN				BIT(3)

#define EMC_SEL_DPD_CTRL_CLK_SEL_DPD_EN				BIT(2)

#define EMC_PRE_REFRESH_REQ_CNT					0x3dc

#define EMC_DYN_SELF_REF_CONTROL				0x3e0

#define EMC_TXSRDLL						0x3e4

#define EMC_TR_RDV_MASK						0x3f8

#define EMC_TR_QSAFE						0x3fc

#define EMC_TR_QRST						0x400

#define EMC_ISSUE_QRST						0x428

#define EMC_AUTO_CAL_CONFIG2					0x458

#define EMC_AUTO_CAL_CONFIG3					0x45c

#define EMC_TR_DVFS						0x460

#define EMC_AUTO_CAL_CHANNEL					0x464

#define EMC_IBDLY						0x468

#define EMC_MRW6						0x4a4

#define EMC_MRW7						0x4a8

#define EMC_MRW8						0x4ac

#define EMC_MRW9						0x4b0

#define EMC_MRW10						0x4b4

#define EMC_MRW11						0x4b8

#define EMC_MRW12						0x4bc

#define EMC_MRW13						0x4c0

#define EMC_MRW14						0x4c4

#define EMC_MRW15						0x4d0

#define EMC_CFG_SYNC						0x4d4

#define EMC_FDPD_CTRL_CMD_NO_RAMP				0x4d8

#define EMC_FDPD_CTRL_CMD_NO_RAMP_CMD_DPD_NO_RAMP_ENABLE	BIT(0)

#define EMC_WDV_CHK						0x4e0

#define EMC_CFG_PIPE_2						0x554

#define EMC_CFG_PIPE_CLK					0x558

#define EMC_CFG_PIPE_CLK_CLK_ALWAYS_ON				BIT(0)

#define EMC_CFG_PIPE_1						0x55c

#define EMC_CFG_PIPE						0x560

#define EMC_QPOP						0x564

#define EMC_QUSE_WIDTH						0x568

#define EMC_PUTERM_WIDTH					0x56c

#define EMC_AUTO_CAL_CONFIG7					0x574

#define EMC_REFCTRL2						0x580

#define EMC_FBIO_CFG7						0x584

#define EMC_FBIO_CFG7_CH0_ENABLE				BIT(1)

#define EMC_CMD_BRLSHFT_2					0x5a4

#define EMC_CMD_BRLSHFT_3					0x5a8

#define EMC_QUSE_BRLSHFT_0					0x5ac

#define EMC_AUTO_CAL_CONFIG4					0x5b0

#define EMC_AUTO_CAL_CONFIG5					0x5b4

#define EMC_QUSE_BRLSHFT_1					0x5b8

#define EMC_QUSE_BRLSHFT_2					0x5bc

#define EMC_CCDMW						0x5c0

#define EMC_QUSE_BRLSHFT_3					0x5c4

#define EMC_AUTO_CAL_CONFIG6					0x5cc

#define EMC_DLL_CFG_0						0x5e4

#define EMC_DLL_CFG_1						0x5e8

#define EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT		10

	(0x7ff << EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT)

#define EMC_CONFIG_SAMPLE_DELAY					0x5f0

#define EMC_CFG_UPDATE						0x5f4

#define EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_SHIFT		9

#define EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_MASK		\

	(0x3 << EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_SHIFT)

#define EMC_PMACRO_QUSE_DDLL_RANK0_0				0x600

#define EMC_PMACRO_QUSE_DDLL_RANK0_1				0x604

#define EMC_PMACRO_QUSE_DDLL_RANK0_2				0x608

#define EMC_PMACRO_DDLL_SHORT_CMD_0				0xc20

#define EMC_PMACRO_DDLL_SHORT_CMD_1				0xc24

#define EMC_PMACRO_DDLL_SHORT_CMD_2				0xc28

#define EMC_PMACRO_CFG_PM_GLOBAL_0				0xc30

#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE0		BIT(16)

#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE1		BIT(17)

#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE2		BIT(18)

#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE3		BIT(19)

#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE4		BIT(20)

#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE5		BIT(21)

#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE6		BIT(22)

#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE7		BIT(23)

#define EMC_PMACRO_VTTGEN_CTRL_0				0xc34

#define EMC_PMACRO_VTTGEN_CTRL_1				0xc38

#define EMC_PMACRO_BG_BIAS_CTRL_0				0xc3c

#define EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD			BIT(0)

#define EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD			BIT(2)

#define EMC_PMACRO_PAD_CFG_CTRL					0xc40

#define EMC_PMACRO_ZCTRL					0xc44

#define EMC_PMACRO_CMD_PAD_RX_CTRL				0xc50

#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_DRVFORCEON		BIT(26)

#define EMC_PMACRO_DATA_PAD_TX_CTRL				0xc64

#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_E_IVREF		BIT(0)

#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_TX_E_DCC		BIT(1)

#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF		BIT(8)

#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSP_TX_E_DCC		BIT(9)

#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC		BIT(16)

#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC		BIT(24)

#define EMC_PMACRO_COMMON_PAD_TX_CTRL				0xc68

#define EMC_PMACRO_AUTOCAL_CFG_COMMON				0xc78

#define EMC_PMACRO_AUTOCAL_CFG_COMMON_E_CAL_BYPASS_DVFS		BIT(16)

#define EMC_PMACRO_VTTGEN_CTRL_2				0xcf0

#define EMC_PMACRO_IB_RXRT					0xcf4

#define EMC_PMACRO_TRAINING_CTRL_0				0xcf8

#define EMC_PMACRO_TRAINING_CTRL_0_CH0_TRAINING_E_WRPTR		BIT(3)

#define EMC_PMACRO_TRAINING_CTRL_1				0xcfc

#define EMC_PMACRO_TRAINING_CTRL_1_CH1_TRAINING_E_WRPTR		BIT(3)

#define EMC_TRAINING_CTRL					0xe04

#define EMC_TRAINING_QUSE_CORS_CTRL				0xe0c

#define EMC_TRAINING_QUSE_FINE_CTRL				0xe10

#define EMC_COPY_TABLE_PARAM_TRIM_REGS				BIT(1)

enum burst_regs_list {

	EMC_RP_INDEX = 6,

	EMC_R2P_INDEX = 9,

	EMC_W2P_INDEX,

	EMC_MRW6_INDEX = 31,

	EMC_REFRESH_INDEX = 41,

	EMC_PRE_REFRESH_REQ_CNT_INDEX = 43,

	EMC_TRPAB_INDEX = 59,

	EMC_MRW7_INDEX = 62,

	EMC_FBIO_CFG5_INDEX = 65,

	EMC_FBIO_CFG7_INDEX,

	EMC_CFG_DIG_DLL_INDEX,

	EMC_ZCAL_INTERVAL_INDEX = 139,

	EMC_ZCAL_WAIT_CNT_INDEX,

	EMC_MRS_WAIT_CNT_INDEX = 141,

	EMC_DLL_CFG_0_INDEX = 144,

	EMC_PMACRO_AUTOCAL_CFG_COMMON_INDEX = 146,

	EMC_CFG_INDEX = 148,

	EMC_DYN_SELF_REF_CONTROL_INDEX = 150,

	EMC_PMACRO_CMD_PAD_TX_CTRL_INDEX = 161,

	EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX,

	EMC_PMACRO_COMMON_PAD_TX_CTRL_INDEX,

	EMC_PMACRO_BRICK_CTRL_RFU1_INDEX = 167,

	EMC_PMACRO_BG_BIAS_CTRL_0_INDEX = 171,

	EMC_MRW14_INDEX = 199,

	EMC_MRW15_INDEX = 220,

};

enum trim_regs_list {

	return result;

}

/* from tegra210-emc-r21021.c */

extern const struct tegra210_emc_sequence tegra210_emc_r21021;

u32 tegra210_emc_mrr_read(struct tegra210_emc *emc, unsigned int chip,

			  unsigned int address);

void tegra210_emc_do_clock_change(struct tegra210_emc *emc, u32 clksrc);