Commit 9b979ac3 authored by Thomas Gleixner's avatar Thomas Gleixner
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Merge tag 'irqchip-5.3' of... 

Merge tag 'irqchip-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

Pull irqchip updates for Linux 5.3 from Marc Zyngier:

 - ACPI support for the exiu and mb86s7x drivers
 - New Renesas RZ/A1, Amazon al-fic drivers
 - Add quirk for Amazon Graviton GICv2m widget
 - Large Renesas driver cleanup
 - CSky mpintc trigger type fixes
 - Meson G12A driver support
 - Various minor cleanups
parents 8afecaa6 3dae67ce

Documentation/devicetree/bindings/interrupt-controller/amazon,al-fic.txt

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Amazon's Annapurna Labs Fabric Interrupt Controller



Required properties:



- compatible: should be "amazon,al-fic"

- reg: physical base address and size of the registers

- interrupt-controller: identifies the node as an interrupt controller

- #interrupt-cells: must be 2.

  First cell defines the index of the interrupt within the controller.

  Second cell is used to specify the trigger type and must be one of the

  following:

    - bits[3:0] trigger type and level flags

	1 = low-to-high edge triggered

	4 = active high level-sensitive

- interrupt-parent: specifies the parent interrupt controller.

- interrupts: describes which input line in the interrupt parent, this

  fic's output is connected to. This field property depends on the parent's

  binding



Example:



amazon_fic: interrupt-controller@0xfd8a8500 {

	compatible = "amazon,al-fic";

	interrupt-controller;

	#interrupt-cells = <2>;

	reg = <0x0 0xfd8a8500 0x0 0x1000>;

	interrupt-parent = <&gic>;

	interrupts = <GIC_SPI 0x0 IRQ_TYPE_LEVEL_HIGH>;

};

Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt

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@@ -15,6 +15,7 @@ Required properties: 
    "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or

    "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)

    "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)

    "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)

- reg : Specifies base physical address and size of the registers.

- interrupt-controller : Identifies the node as an interrupt controller.

- #interrupt-cells : Specifies the number of cells needed to encode an

Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt

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@@ -6,11 +6,16 @@ C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860 
SMP soc, and it also could be used in non-SMP system.



Interrupt number definition:



  0-15  : software irq, and we use 15 as our IPI_IRQ.

 16-31  : private  irq, and we use 16 as the co-processor timer.

 31-1024: common irq for soc ip.



Interrupt triger mode: (Defined in dt-bindings/interrupt-controller/irq.h)

 IRQ_TYPE_LEVEL_HIGH (default)

 IRQ_TYPE_LEVEL_LOW

 IRQ_TYPE_EDGE_RISING

 IRQ_TYPE_EDGE_FALLING



=============================

intc node bindings definition

=============================
@@ -26,15 +31,22 @@ intc node bindings definition 
	- #interrupt-cells

		Usage: required

		Value type: <u32>

		Definition: must be <1>

		Definition: <2>

	- interrupt-controller:

		Usage: required



Examples:

Examples: ("interrupts = <irq_num IRQ_TYPE_XXX>")

---------

#include <dt-bindings/interrupt-controller/irq.h>



	intc: interrupt-controller {

		compatible = "csky,mpintc";

		#interrupt-cells = <1>;

		#interrupt-cells = <2>;

		interrupt-controller;

	};



	device: device-example {

		...

		interrupts = <34 IRQ_TYPE_EDGE_RISING>;

		interrupt-parent = <&intc>;

	};

Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt

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DT bindings for the Renesas RZ/A1 Interrupt Controller



The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas

RZ/A1 and RZ/A2 SoCs:

  - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI

    interrupts,

  - NMI edge select.



Required properties:

  - compatible: Must be "renesas,<soctype>-irqc", and "renesas,rza1-irqc" as

		fallback.

		Examples with soctypes are:

		  - "renesas,r7s72100-irqc" (RZ/A1H)

		  - "renesas,r7s9210-irqc" (RZ/A2M)

  - #interrupt-cells: Must be 2 (an interrupt index and flags, as defined

				 in interrupts.txt in this directory)

  - #address-cells: Must be zero

  - interrupt-controller: Marks the device as an interrupt controller

  - reg: Base address and length of the memory resource used by the interrupt

         controller

  - interrupt-map: Specifies the mapping from external interrupts to GIC

		   interrupts

  - interrupt-map-mask: Must be <7 0>



Example:



	irqc: interrupt-controller@fcfef800 {

		compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";

		#interrupt-cells = <2>;

		#address-cells = <0>;

		interrupt-controller;

		reg = <0xfcfef800 0x6>;

		interrupt-map =

			<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

			<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

			<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,

			<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

			<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

			<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,

			<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

			<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-map-mask = <7 0>;

	};

MAINTAINERS

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@@ -1304,6 +1304,12 @@ S: Maintained 
F:	Documentation/devicetree/bindings/interrupt-controller/arm,vic.txt

F:	drivers/irqchip/irq-vic.c



AMAZON ANNAPURNA LABS FIC DRIVER

M:	Talel Shenhar <talel@amazon.com>

S:	Maintained

F:	Documentation/devicetree/bindings/interrupt-controller/amazon,al-fic.txt

F:	drivers/irqchip/irq-al-fic.c



ARM SMMU DRIVERS

M:	Will Deacon <will.deacon@arm.com>

R:	Robin Murphy <robin.murphy@arm.com>

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