Commit 9b83d851 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'xtensa-next-20140123' of git://github.com/czankel/xtensa-linux 

Pull Xtensa patches from Chris Zankel:
 "The major changes are adding support for SMP for Xtensa, fixing and
  cleaning up the ISS (simulator) network driver, and better support for
  device trees"

* tag 'xtensa-next-20140123' of git://github.com/czankel/xtensa-linux: (40 commits)
  xtensa: implement ndelay
  xtensa: clean up udelay
  xtensa: enable HAVE_PERF_EVENTS
  xtensa: remap io area defined in device tree
  xtensa: support default device tree buses
  xtensa: initialize device tree clock sources
  xtensa: xtfpga: fix definitions of platform devices
  xtensa: standardize devicetree cpu compatible strings
  xtensa: avoid duplicate of IO range definitions
  xtensa: fix ATOMCTL register documentation
  xtensa: Enable irqs after cpu is set online
  xtensa: ISS: raise network polling rate to 10 times/sec
  xtensa: remove unused XTENSA_ISS_NETWORK Kconfig parameter
  xtensa: ISS: avoid simple_strtoul usage
  xtensa: Switch to sched_clock_register()
  xtensa: implement CPU hotplug
  xtensa: add SMP support
  xtensa: add MX irqchip
  xtensa: clear timer IRQ unconditionally in its handler
  xtensa: clean up do_interrupt/do_IRQ
  ...
parents 2d08cd0e 9ed82c68

Documentation/xtensa/atomctl.txt

+1 −1
Original line number Diff line number Diff line
@@ -40,5 +40,5 @@ See Section 4.3.12.4 of ISA; Bits: 
---------    ---------------         -----------------     ----------------

    0        Exception               Exception               Exception

    1        RCW Transaction         RCW Transaction         RCW Transaction

    2        Internal Operation      Exception               Reserved

    2        Internal Operation      Internal Operation      Reserved

    3        Reserved                Reserved                Reserved

Documentation/xtensa/mmu.txt

+18 −0
Original line number Diff line number Diff line
@@ -44,3 +44,21 @@ After step 4, we jump to intended (linked) address of this code. 
 40..5F -> 40         40..5F -> pc  -> pc  40..5F -> pc

 20..3F -> 20  -> 20  20..3F -> 20

 00..1F -> 00  -> 00  00..1F -> 00



The default location of IO peripherals is above 0xf0000000. This may change

using a "ranges" property in a device tree simple-bus node. See ePAPR 1.1, §6.5

for details on the syntax and semantic of simple-bus nodes. The following

limitations apply:



1. Only top level simple-bus nodes are considered



2. Only one (first) simple-bus node is considered



3. Empty "ranges" properties are not supported



4. Only the first triplet in the "ranges" property is considered



5. The parent-bus-address value is rounded down to the nearest 256MB boundary



6. The IO area covers the entire 256MB segment of parent-bus-address; the

   "ranges" triplet length field is ignored

arch/xtensa/Kconfig

+47 −5
Original line number Diff line number Diff line
@@ -9,7 +9,6 @@ config XTENSA 
	select GENERIC_CLOCKEVENTS

	select VIRT_TO_BUS

	select GENERIC_IRQ_SHOW

	select GENERIC_CPU_DEVICES

	select GENERIC_SCHED_CLOCK

	select MODULES_USE_ELF_RELA

	select GENERIC_PCI_IOMAP
@@ -19,6 +18,8 @@ config XTENSA 
	select IRQ_DOMAIN

	select HAVE_OPROFILE

	select HAVE_FUNCTION_TRACER

	select HAVE_IRQ_TIME_ACCOUNTING

	select HAVE_PERF_EVENTS

	help

	  Xtensa processors are 32-bit RISC machines designed by Tensilica

	  primarily for embedded systems.  These processors are both
@@ -67,6 +68,9 @@ config VARIANT_IRQ_SWITCH 
config HAVE_XTENSA_GPIO32

	def_bool n



config MAY_HAVE_SMP

	def_bool n



menu "Processor type and features"



choice
@@ -110,6 +114,48 @@ config XTENSA_UNALIGNED_USER 


source "kernel/Kconfig.preempt"



config HAVE_SMP

	bool "System Supports SMP (MX)"

	depends on MAY_HAVE_SMP

	select XTENSA_MX

	help

	  This option is use to indicate that the system-on-a-chip (SOC)

	  supports Multiprocessing. Multiprocessor support implemented above

	  the CPU core definition and currently needs to be selected manually.



	  Multiprocessor support in implemented with external cache and

	  interrupt controlers.



	  The MX interrupt distributer adds Interprocessor Interrupts

	  and causes the IRQ numbers to be increased by 4 for devices

	  like the open cores ethernet driver and the serial interface.



	  You still have to select "Enable SMP" to enable SMP on this SOC.



config SMP

	bool "Enable Symmetric multi-processing support"

	depends on HAVE_SMP

	select USE_GENERIC_SMP_HELPERS

	select GENERIC_SMP_IDLE_THREAD

	help

	  Enabled SMP Software; allows more than one CPU/CORE

	  to be activated during startup.



config NR_CPUS

	depends on SMP

	int "Maximum number of CPUs (2-32)"

	range 2 32

	default "4"



config HOTPLUG_CPU

	bool "Enable CPU hotplug support"

	depends on SMP

	help

	  Say Y here to allow turning CPUs off and on. CPUs can be

	  controlled through /sys/devices/system/cpu.



	  Say N if you want to disable CPU hotplug.



config MATH_EMULATION

	bool "Math emulation"

	help
@@ -156,9 +202,6 @@ config XTENSA_CALIBRATE_CCOUNT 
config SERIAL_CONSOLE

	def_bool n



config XTENSA_ISS_NETWORK

	def_bool n



menu "Bus options"



config PCI
@@ -185,7 +228,6 @@ config XTENSA_PLATFORM_ISS 
	depends on TTY

	select XTENSA_CALIBRATE_CCOUNT

	select SERIAL_CONSOLE

	select XTENSA_ISS_NETWORK

	help

	  ISS is an acronym for Tensilica's Instruction Set Simulator.

arch/xtensa/boot/dts/lx60.dts

+1 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
/include/ "xtfpga-flash-4m.dtsi"



/ {

	compatible = "xtensa,lx60";

	compatible = "cdns,xtensa-lx60";

	memory@0 {

		device_type = "memory";

		reg = <0x00000000 0x04000000>;

arch/xtensa/boot/dts/ml605.dts

+1 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
/include/ "xtfpga-flash-16m.dtsi"



/ {

	compatible = "xtensa,ml605";

	compatible = "cdns,xtensa-ml605";

	memory@0 {

		device_type = "memory";

		reg = <0x00000000 0x08000000>;

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