Merge branch 'irq/ipi-as-irq', remote-tracking branches 'origin/irq/dw' and...

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/actions,owl-sirq.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Actions Semi Owl SoCs SIRQ interrupt controller

maintainers:

  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

  - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

description: |

  This interrupt controller is found in the Actions Semi Owl SoCs (S500, S700

  and S900) and provides support for handling up to 3 external interrupt lines.

properties:

  compatible:

    enum:

      - actions,s500-sirq

      - actions,s700-sirq

      - actions,s900-sirq

  reg:

    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':

    const: 2

    description:

      The first cell is the input IRQ number, between 0 and 2, while the second

      cell is the trigger type as defined in interrupt.txt in this directory.

  'interrupts':

    description: |

      Contains the GIC SPI IRQs mapped to the external interrupt lines.

      They shall be specified sequentially from output 0 to 2.

    minItems: 3

    maxItems: 3

required:

  - compatible

  - reg

  - interrupt-controller

  - '#interrupt-cells'

  - 'interrupts'

additionalProperties: false

examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    sirq: interrupt-controller@b01b0200 {

      compatible = "actions,s500-sirq";

      reg = <0xb01b0200 0x4>;

      interrupt-controller;

      #interrupt-cells = <2>;

      interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ0 */

                   <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ1 */

                   <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; /* SIRQ2 */

    };

...

Synopsys DesignWare provides interrupt controller IP for APB known as

dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with

APB bus, e.g. Marvell Armada 1500.

APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt

controller in some SoCs, e.g. Hisilicon SD5203.

Required properties:

- compatible: shall be "snps,dw-apb-ictl"

  region starting with ENABLE_LOW register

- interrupt-controller: identifies the node as an interrupt controller

- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1

Additional required property when it's used as secondary interrupt controller:

- interrupts: interrupt reference to primary interrupt controller

The interrupt sources map to the corresponding bits in the interrupt

- (optional) fast interrupts start at 64.

Example:

	/* dw_apb_ictl is used as secondary interrupt controller */

	aic: interrupt-controller@3000 {

		compatible = "snps,dw-apb-ictl";

		reg = <0x3000 0xc00>;

		interrupt-parent = <&gic>;

		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;

	};

	/* dw_apb_ictl is used as primary interrupt controller */

	vic: interrupt-controller@10130000 {

		compatible = "snps,dw-apb-ictl";

		reg = <0x10130000 0x1000>;

		interrupt-controller;

		#interrupt-cells = <1>;

	};

F:	Documentation/devicetree/bindings/clock/actions,owl-cmu.txt

F:	Documentation/devicetree/bindings/dma/owl-dma.txt

F:	Documentation/devicetree/bindings/i2c/i2c-owl.txt

F:	Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml

F:	Documentation/devicetree/bindings/mmc/owl-mmc.yaml

F:	Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt

F:	Documentation/devicetree/bindings/power/actions,owl-sps.txt

F:	drivers/clocksource/timer-owl*

F:	drivers/dma/owl-dma.c

F:	drivers/i2c/busses/i2c-owl.c

F:	drivers/irqchip/irq-owl-sirq.c

F:	drivers/mmc/host/owl-mmc.c

F:	drivers/pinctrl/actions/*

F:	drivers/soc/actions/

static struct irq_desc *ipi_desc[MAX_IPI] __read_mostly;

static void ipi_setup(int cpu);

static void ipi_teardown(int cpu);

static DECLARE_COMPLETION(cpu_running);

	return cpu != 0;

}

static void ipi_teardown(int cpu)

{

	int i;

	if (WARN_ON_ONCE(!ipi_irq_base))

		return;

	for (i = 0; i < nr_ipi; i++)

		disable_percpu_irq(ipi_irq_base + i);

}

/*

 * __cpu_disable runs on the processor to be shutdown.

 */

	unsigned int cpu, i;

	for (i = 0; i < NR_IPI; i++) {

		unsigned int irq = irq_desc_get_irq(ipi_desc[i]);

		unsigned int irq;

		if (!ipi_desc[i])

			continue;

		irq = irq_desc_get_irq(ipi_desc[i]);

		seq_printf(p, "%*s%u: ", prec - 1, "IPI", i);

		for_each_online_cpu(cpu)

		enable_percpu_irq(ipi_irq_base + i, 0);

}

static void ipi_teardown(int cpu)

{

	int i;

	if (WARN_ON_ONCE(!ipi_irq_base))

		return;

	for (i = 0; i < nr_ipi; i++)

		disable_percpu_irq(ipi_irq_base + i);

}

void __init set_smp_ipi_range(int ipi_base, int n)

{

	int i;

static struct irq_desc *ipi_desc[NR_IPI] __read_mostly;

static void ipi_setup(int cpu);

static void ipi_teardown(int cpu);

#ifdef CONFIG_HOTPLUG_CPU

static void ipi_teardown(int cpu);

static int op_cpu_kill(unsigned int cpu);

#else

static inline int op_cpu_kill(unsigned int cpu)

		enable_percpu_irq(ipi_irq_base + i, 0);

}

#ifdef CONFIG_HOTPLUG_CPU

static void ipi_teardown(int cpu)

{

	int i;

	for (i = 0; i < nr_ipi; i++)

		disable_percpu_irq(ipi_irq_base + i);

}

#endif

void __init set_smp_ipi_range(int ipi_base, int n)

{