Merge tag 'uniphier-dt64-v4.9' of... (9b2a8b8b) · Commits · 戴 / test

arch/arm64/boot/dts/socionext/Makefile

+3 −1

Original line number	Diff line number	Diff line
		dtb-$(CONFIG_ARCH_UNIPHIER) += uniphier-ph1-ld20-ref.dtb
		dtb-$(CONFIG_ARCH_UNIPHIER) += \
		uniphier-ld11-ref.dtb \
		uniphier-ld20-ref.dtb

		always := $(dtb-y)
		clean-files := *.dtb

arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts

0 → 100644

+100 −0

Original line number	Diff line number	Diff line
		/*
		* Device Tree Source for UniPhier LD11 Reference Board
		*
		* Copyright (C) 2016 Socionext Inc.
		* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
		*
		* This file is dual-licensed: you can use it either under the terms
		* of the GPL or the X11 license, at your option. Note that this dual
		* licensing only applies to this file, and not this project as a
		* whole.
		*
		* a) This file is free software; you can redistribute it and/or
		* modify it under the terms of the GNU General Public License as
		* published by the Free Software Foundation; either version 2 of the
		* License, or (at your option) any later version.
		*
		* This file is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*
		* Or, alternatively,
		*
		* b) Permission is hereby granted, free of charge, to any person
		* obtaining a copy of this software and associated documentation
		* files (the "Software"), to deal in the Software without
		* restriction, including without limitation the rights to use,
		* copy, modify, merge, publish, distribute, sublicense, and/or
		* sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following
		* conditions:
		*
		* The above copyright notice and this permission notice shall be
		* included in all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
		* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
		* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
		* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
		* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
		* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		* OTHER DEALINGS IN THE SOFTWARE.
		*/

		/dts-v1/;
		/include/ "uniphier-ld11.dtsi"
		/include/ "uniphier-ref-daughter.dtsi"
		/include/ "uniphier-support-card.dtsi"

		/ {
		model = "UniPhier LD11 Reference Board";
		compatible = "socionext,uniphier-ld11-ref", "socionext,uniphier-ld11";

		memory {
		device_type = "memory";
		reg = <0 0x80000000 0 0x40000000>;
		};

		chosen {
		stdout-path = "serial0:115200n8";
		};

		aliases {
		serial0 = &serial0;
		serial1 = &serial1;
		serial2 = &serial2;
		serial3 = &serial3;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		};
		};

		&ethsc {
		interrupts = <0 48 4>;
		};

		&serial0 {
		status = "okay";
		};

		&i2c0 {
		status = "okay";
		};

		&usb0 {
		status = "okay";
		};

		&usb1 {
		status = "okay";
		};

		&usb2 {
		status = "okay";
		};

arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi

0 → 100644

+338 −0

Original line number	Diff line number	Diff line
		/*
		* Device Tree Source for UniPhier LD11 SoC
		*
		* Copyright (C) 2016 Socionext Inc.
		* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
		*
		* This file is dual-licensed: you can use it either under the terms
		* of the GPL or the X11 license, at your option. Note that this dual
		* licensing only applies to this file, and not this project as a
		* whole.
		*
		* a) This file is free software; you can redistribute it and/or
		* modify it under the terms of the GNU General Public License as
		* published by the Free Software Foundation; either version 2 of the
		* License, or (at your option) any later version.
		*
		* This file is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*
		* Or, alternatively,
		*
		* b) Permission is hereby granted, free of charge, to any person
		* obtaining a copy of this software and associated documentation
		* files (the "Software"), to deal in the Software without
		* restriction, including without limitation the rights to use,
		* copy, modify, merge, publish, distribute, sublicense, and/or
		* sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following
		* conditions:
		*
		* The above copyright notice and this permission notice shall be
		* included in all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
		* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
		* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
		* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
		* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
		* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		* OTHER DEALINGS IN THE SOFTWARE.
		*/

		/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */

		/ {
		compatible = "socionext,uniphier-ld11";
		#address-cells = <2>;
		#size-cells = <2>;
		interrupt-parent = <&gic>;

		cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
		cluster0 {
		core0 {
		cpu = <&cpu0>;
		};
		core1 {
		cpu = <&cpu1>;
		};
		};
		};

		cpu0: cpu@0 {
		device_type = "cpu";
		compatible = "arm,cortex-a53", "arm,armv8";
		reg = <0 0x000>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x80000000>;
		};

		cpu1: cpu@1 {
		device_type = "cpu";
		compatible = "arm,cortex-a53", "arm,armv8";
		reg = <0 0x001>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x80000000>;
		};
		};

		clocks {
		refclk: ref {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
		};
		};

		timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 4>,
		<1 14 4>,
		<1 11 4>,
		<1 10 4>;
		};

		soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;

		serial0: serial@54006800 {
		compatible = "socionext,uniphier-uart";
		status = "disabled";
		reg = <0x54006800 0x40>;
		interrupts = <0 33 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_uart0>;
		clocks = <&peri_clk 0>;
		};

		serial1: serial@54006900 {
		compatible = "socionext,uniphier-uart";
		status = "disabled";
		reg = <0x54006900 0x40>;
		interrupts = <0 35 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_uart1>;
		clocks = <&peri_clk 1>;
		};

		serial2: serial@54006a00 {
		compatible = "socionext,uniphier-uart";
		status = "disabled";
		reg = <0x54006a00 0x40>;
		interrupts = <0 37 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_uart2>;
		clocks = <&peri_clk 2>;
		};

		serial3: serial@54006b00 {
		compatible = "socionext,uniphier-uart";
		status = "disabled";
		reg = <0x54006b00 0x40>;
		interrupts = <0 177 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_uart3>;
		clocks = <&peri_clk 3>;
		};

		i2c0: i2c@58780000 {
		compatible = "socionext,uniphier-fi2c";
		status = "disabled";
		reg = <0x58780000 0x80>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <0 41 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c0>;
		clocks = <&peri_clk 4>;
		clock-frequency = <100000>;
		};

		i2c1: i2c@58781000 {
		compatible = "socionext,uniphier-fi2c";
		status = "disabled";
		reg = <0x58781000 0x80>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <0 42 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c1>;
		clocks = <&peri_clk 5>;
		clock-frequency = <100000>;
		};

		i2c2: i2c@58782000 {
		compatible = "socionext,uniphier-fi2c";
		reg = <0x58782000 0x80>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <0 43 4>;
		clocks = <&peri_clk 6>;
		clock-frequency = <400000>;
		};

		i2c3: i2c@58783000 {
		compatible = "socionext,uniphier-fi2c";
		status = "disabled";
		reg = <0x58783000 0x80>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <0 44 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c3>;
		clocks = <&peri_clk 7>;
		clock-frequency = <100000>;
		};

		i2c4: i2c@58784000 {
		compatible = "socionext,uniphier-fi2c";
		status = "disabled";
		reg = <0x58784000 0x80>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <0 45 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c4>;
		clocks = <&peri_clk 8>;
		clock-frequency = <100000>;
		};

		i2c5: i2c@58785000 {
		compatible = "socionext,uniphier-fi2c";
		reg = <0x58785000 0x80>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <0 25 4>;
		clocks = <&peri_clk 9>;
		clock-frequency = <400000>;
		};

		system_bus: system-bus@58c00000 {
		compatible = "socionext,uniphier-system-bus";
		status = "disabled";
		reg = <0x58c00000 0x400>;
		#address-cells = <2>;
		#size-cells = <1>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_system_bus>;
		};

		smpctrl@59800000 {
		compatible = "socionext,uniphier-smpctrl";
		reg = <0x59801000 0x400>;
		};

		perictrl@59820000 {
		compatible = "socionext,uniphier-perictrl",
		"simple-mfd", "syscon";
		reg = <0x59820000 0x200>;

		peri_clk: clock {
		compatible = "socionext,uniphier-ld11-peri-clock";
		#clock-cells = <1>;
		};

		peri_rst: reset {
		compatible = "socionext,uniphier-ld11-peri-reset";
		#reset-cells = <1>;
		};
		};

		usb0: usb@5a800100 {
		compatible = "socionext,uniphier-ehci", "generic-ehci";
		status = "disabled";
		reg = <0x5a800100 0x100>;
		interrupts = <0 243 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb0>;
		clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
		resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>;
		};

		usb1: usb@5a810100 {
		compatible = "socionext,uniphier-ehci", "generic-ehci";
		status = "disabled";
		reg = <0x5a810100 0x100>;
		interrupts = <0 244 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb1>;
		clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
		resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>;
		};

		usb2: usb@5a820100 {
		compatible = "socionext,uniphier-ehci", "generic-ehci";
		status = "disabled";
		reg = <0x5a820100 0x100>;
		interrupts = <0 245 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb2>;
		clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
		resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>;
		};

		mioctrl@5b3e0000 {
		compatible = "socionext,uniphier-mioctrl",
		"simple-mfd", "syscon";
		reg = <0x5b3e0000 0x800>;

		mio_clk: clock {
		compatible = "socionext,uniphier-ld11-mio-clock";
		#clock-cells = <1>;
		};

		mio_rst: reset {
		compatible = "socionext,uniphier-ld11-mio-reset";
		#reset-cells = <1>;
		resets = <&sys_rst 7>;
		};
		};

		soc-glue@5f800000 {
		compatible = "socionext,uniphier-soc-glue",
		"simple-mfd", "syscon";
		reg = <0x5f800000 0x2000>;

		pinctrl: pinctrl {
		compatible = "socionext,uniphier-ld11-pinctrl";
		};
		};

		gic: interrupt-controller@5fe00000 {
		compatible = "arm,gic-v3";
		reg = <0x5fe00000 0x10000>, /* GICD */
		<0x5fe40000 0x80000>; /* GICR */
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupts = <1 9 4>;
		};

		sysctrl@61840000 {
		compatible = "socionext,uniphier-ld11-sysctrl",
		"simple-mfd", "syscon";
		reg = <0x61840000 0x4000>;

		sys_clk: clock {
		compatible = "socionext,uniphier-ld11-clock";
		#clock-cells = <1>;
		};

		sys_rst: reset {
		compatible = "socionext,uniphier-ld11-reset";
		#reset-cells = <1>;
		};
		};
		};
		};

		/include/ "uniphier-pinctrl.dtsi"

arch/arm64/boot/dts/socionext/uniphier-ph1-ld20-ref.dts→arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts

+6 −5

Original line number	Diff line number	Diff line
		/*
		* Device Tree Source for UniPhier PH1-LD20 Reference Board
		* Device Tree Source for UniPhier LD20 Reference Board
		*
		* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
		* Copyright (C) 2015-2016 Socionext Inc.
		* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
		*
		* This file is dual-licensed: you can use it either under the terms
		* of the GPL or the X11 license, at your option. Note that this dual
		@@ -43,13 +44,13 @@
		*/

		/dts-v1/;
		/include/ "uniphier-ph1-ld20.dtsi"
		/include/ "uniphier-ld20.dtsi"
		/include/ "uniphier-ref-daughter.dtsi"
		/include/ "uniphier-support-card.dtsi"

		/ {
		model = "UniPhier PH1-LD20 Reference Board";
		compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20";
		model = "UniPhier LD20 Reference Board";
		compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";

		memory {
		device_type = "memory";

arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi→arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi

+67 −27

Original line number	Diff line number	Diff line
		/*
		* Device Tree Source for UniPhier PH1-LD20 SoC
		* Device Tree Source for UniPhier LD20 SoC
		*
		* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
		* Copyright (C) 2015-2016 Socionext Inc.
		* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
		*
		* This file is dual-licensed: you can use it either under the terms
		* of the GPL or the X11 license, at your option. Note that this dual
		@@ -45,7 +46,7 @@
		/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */

		/ {
		compatible = "socionext,ph1-ld20";
		compatible = "socionext,uniphier-ld20";
		#address-cells = <2>;
		#size-cells = <2>;
		interrupt-parent = <&gic>;
		@@ -113,18 +114,6 @@
		#clock-cells = <0>;
		clock-frequency = <25000000>;
		};

		uart_clk: uart_clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <58820000>;
		};

		i2c_clk: i2c_clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <50000000>;
		};
		};

		timer {
		@@ -148,7 +137,7 @@
		interrupts = <0 33 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_uart0>;
		clocks = <&uart_clk>;
		clocks = <&peri_clk 0>;
		};

		serial1: serial@54006900 {
		@@ -158,7 +147,7 @@
		interrupts = <0 35 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_uart1>;
		clocks = <&uart_clk>;
		clocks = <&peri_clk 1>;
		};

		serial2: serial@54006a00 {
		@@ -168,7 +157,7 @@
		interrupts = <0 37 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_uart2>;
		clocks = <&uart_clk>;
		clocks = <&peri_clk 2>;
		};

		serial3: serial@54006b00 {
		@@ -178,7 +167,7 @@
		interrupts = <0 177 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_uart3>;
		clocks = <&uart_clk>;
		clocks = <&peri_clk 3>;
		};

		i2c0: i2c@58780000 {
		@@ -190,7 +179,7 @@
		interrupts = <0 41 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c0>;
		clocks = <&i2c_clk>;
		clocks = <&peri_clk 4>;
		clock-frequency = <100000>;
		};

		@@ -203,7 +192,7 @@
		interrupts = <0 42 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c1>;
		clocks = <&i2c_clk>;
		clocks = <&peri_clk 5>;
		clock-frequency = <100000>;
		};

		@@ -213,7 +202,7 @@
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <0 43 4>;
		clocks = <&i2c_clk>;
		clocks = <&peri_clk 6>;
		clock-frequency = <400000>;
		};

		@@ -226,7 +215,7 @@
		interrupts = <0 44 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c3>;
		clocks = <&i2c_clk>;
		clocks = <&peri_clk 7>;
		clock-frequency = <100000>;
		};

		@@ -239,7 +228,7 @@
		interrupts = <0 45 4>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c4>;
		clocks = <&i2c_clk>;
		clocks = <&peri_clk 8>;
		clock-frequency = <100000>;
		};

		@@ -249,7 +238,7 @@
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <0 25 4>;
		clocks = <&i2c_clk>;
		clocks = <&peri_clk 9>;
		clock-frequency = <400000>;
		};

		@@ -259,6 +248,8 @@
		reg = <0x58c00000 0x400>;
		#address-cells = <2>;
		#size-cells = <1>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_system_bus>;
		};

		smpctrl@59800000 {
		@@ -266,8 +257,41 @@
		reg = <0x59801000 0x400>;
		};

		mioctrl@59810000 {
		compatible = "socionext,uniphier-mioctrl",
		"simple-mfd", "syscon";
		reg = <0x59810000 0x800>;

		mio_clk: clock {
		compatible = "socionext,uniphier-ld20-mio-clock";
		#clock-cells = <1>;
		};

		mio_rst: reset {
		compatible = "socionext,uniphier-ld20-mio-reset";
		#reset-cells = <1>;
		};
		};

		perictrl@59820000 {
		compatible = "socionext,uniphier-perictrl",
		"simple-mfd", "syscon";
		reg = <0x59820000 0x200>;

		peri_clk: clock {
		compatible = "socionext,uniphier-ld20-peri-clock";
		#clock-cells = <1>;
		};

		peri_rst: reset {
		compatible = "socionext,uniphier-ld20-peri-reset";
		#reset-cells = <1>;
		};
		};

		soc-glue@5f800000 {
		compatible = "simple-mfd", "syscon";
		compatible = "socionext,uniphier-soc-glue",
		"simple-mfd", "syscon";
		reg = <0x5f800000 0x2000>;

		pinctrl: pinctrl {
		@@ -283,6 +307,22 @@
		#interrupt-cells = <3>;
		interrupts = <1 9 4>;
		};

		sysctrl@61840000 {
		compatible = "socionext,uniphier-sysctrl",
		"simple-mfd", "syscon";
		reg = <0x61840000 0x4000>;

		sys_clk: clock {
		compatible = "socionext,uniphier-ld20-clock";
		#clock-cells = <1>;
		};

		sys_rst: reset {
		compatible = "socionext,uniphier-ld20-reset";
		#reset-cells = <1>;
		};
		};
		};
		};

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