Merge tag 'mac80211-next-for-davem-2015-12-07' into next

What:		/sys/bus/scsi/drivers/st/debug_flag

Date:		October 2015

Kernel Version:	?.?

Contact:	shane.seymour@hpe.com

Description:

		This file allows you to turn debug output from the st driver

		off if you write a '0' to the file or on if you write a '1'.

		Note that debug output requires that the module be compiled

		with the #define DEBUG set to a non-zero value (this is the

		default). If DEBUG is set to 0 then this file will not

		appear in sysfs as its presence is conditional upon debug

		output support being compiled into the module.

See more details on the proper patch format in the following

references.

15) Explicit In-Reply-To headers

--------------------------------

It can be helpful to manually add In-Reply-To: headers to a patch

(e.g., when using "git send email") to associate the patch with

previous relevant discussion, e.g. to link a bug fix to the email with

the bug report.  However, for a multi-patch series, it is generally

best to avoid using In-Reply-To: to link to older versions of the

series.  This way multiple versions of the patch don't become an

unmanageable forest of references in email clients.  If a link is

helpful, you can use the https://lkml.kernel.org/ redirector (e.g., in

the cover email text) to link to an earlier version of the patch series.

15) Sending "git pull" requests

16) Sending "git pull" requests

-------------------------------

If you have a series of patches, it may be most convenient to have the

* Texas Instruments tsc2005 touchscreen controller

* Texas Instruments tsc2004 and tsc2005 touchscreen controllers

Required properties:

 - compatible		      : "ti,tsc2005"

 - reg			      : SPI device address

 - spi-max-frequency	      : Maximal SPI speed

 - compatible		      : "ti,tsc2004" or "ti,tsc2005"

 - reg			      : Device address

 - interrupts		      : IRQ specifier

 - reset-gpios		      : GPIO specifier

 - vio-supply                 : Regulator specifier

 - spi-max-frequency	      : Maximum SPI clocking speed of the device

			        (for tsc2005)

Optional properties:

 - vio-supply		      : Regulator specifier

 - reset-gpios		      : GPIO specifier for the controller reset line

 - ti,x-plate-ohms	      : integer, resistance of the touchscreen's X plates

				in ohm (defaults to 280)

 - ti,esd-recovery-timeout-ms : integer, if the touchscreen does not respond after

Example:

&i2c3 {

	tsc2004@48 {

		compatible = "ti,tsc2004";

		reg = <0x48>;

		vio-supply = <&vio>;

		reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;

		interrupts-extended = <&gpio1 27 IRQ_TYPE_EDGE_RISING>;

		touchscreen-fuzz-x = <4>;

		touchscreen-fuzz-y = <7>;

		touchscreen-fuzz-pressure = <2>;

		touchscreen-size-x = <4096>;

		touchscreen-size-y = <4096>;

		touchscreen-max-pressure = <2048>;

		ti,x-plate-ohms = <280>;

		ti,esd-recovery-timeout-ms = <8000>;

	};

}

&mcspi1 {

	tsc2005@0 {

		compatible = "ti,tsc2005";

Imagination University Program MIPSfpga

=======================================

Under the Imagination University Program, a microAptiv UP core has been

released for academic usage.

As we are dealing with a MIPS core instantiated on an FPGA, specifications

are fluid and can be varied in RTL.

This binding document is provided as baseline guidance for the example

project provided by IMG.

The example project runs on the Nexys4DDR board by Digilent powered by

the ARTIX-7 FPGA by Xilinx.

Relevant details about the example project and the Nexys4DDR board:

- microAptiv UP core m14Kc

- 50MHz clock speed

- 128Mbyte DDR RAM	at 0x0000_0000

- 8Kbyte RAM		at 0x1000_0000

- axi_intc		at 0x1020_0000

- axi_uart16550		at 0x1040_0000

- axi_gpio		at 0x1060_0000

- axi_i2c		at 0x10A0_0000

- custom_gpio		at 0x10C0_0000

- axi_ethernetlite	at 0x10E0_0000

- 8Kbyte BootRAM	at 0x1FC0_0000

Required properties:

--------------------

 - compatible: Must include "digilent,nexys4ddr","img,xilfpga".

CPU nodes:

----------

A "cpus" node is required.  Required properties:

 - #address-cells: Must be 1.

 - #size-cells: Must be 0.

A CPU sub-node is also required for at least CPU 0. Required properties:

 - device_type: Must be "cpu".

 - compatible: Must be "mips,m14Kc".

 - reg: Must be <0>.

 - clocks: phandle to ext clock for fixed-clock received by MIPS core.

Example:

	compatible = "img,xilfpga","digilent,nexys4ddr";

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "mips,m14Kc";

			reg = <0>;

			clocks	= <&ext>;

		};

	};

	ext: ext {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <50000000>;

	};

Boot protocol:

--------------

The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000.

This is for easy reprogrammibility via JTAG.

The BootRAM initializes the cache and the axi_uart peripheral.

DDR initialization is already handled by a HW IP block.

When the example project bitstream is loaded, the cpu_reset button

needs to be pressed.

The bootram initializes the cache and axi_uart.

Then outputs MIPSFPGA\n\r on the serial port on the Nexys4DDR board.

At this point, the board is ready to load the Linux kernel

vmlinux file via JTAG.

			  switch. Must be set if the switch can not detect

			  the presence and/or size of a connected EEPROM,

			  otherwise optional.

- reset-gpios		: phandle and specifier to a gpio line connected to

			  reset pin of the switch chip.

A switch may have multiple "port" children nodes

			#size-cells = <0>;

			reg = <17 1>;	/* MDIO address 17, switch 1 in tree */

			mii-bus = <&mii_bus1>;

			reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;

			switch1port0: port@0 {

				reg = <0>;