Commit 9b11bbf0 authored Mar 04, 2020 by Tvrtko Ursulin

drm/i915/tgl: WaDisableGPGPUMidThreadPreemption



Enable FtrPerCtxtPreemptionGranularityControl bit and select thread-
group as the default preemption level.

v2:
 * Remove register whitelisting (Rafael, Tony).

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: piotr.zdunowski@intel.com
Cc: michal.mrozek@intel.com
Cc: Tony Ye <tony.ye@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Acked-by: Rafael Antognolli <rafael.antognolli@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Tony Ye <tony.ye@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200304153144.10675-1-tvrtko.ursulin@linux.intel.com

parent be90e344

drivers/gpu/drm/i915/gt/intel_workarounds.c

+7 −2

Original line number	Diff line number	Diff line
		@@ -601,6 +601,11 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
		*/
		wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
		FF_MODE2_TDS_TIMER_128, 0);

		/* WaDisableGPGPUMidThreadPreemption:tgl */
		WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
		GEN9_PREEMPT_GPGPU_LEVEL_MASK,
		GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
		}

		static void
		@@ -1475,8 +1480,8 @@ rcs_engine_wa_init(struct intel_engine_cs engine, struct i915_wa_list wal)
		PSDUNIT_CLKGATE_DIS);
		}

		if (IS_GEN_RANGE(i915, 9, 11)) {
		/* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl */
		if (IS_GEN_RANGE(i915, 9, 12)) {
		/* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
		wa_masked_en(wal,
		GEN7_FF_SLICE_CS_CHICKEN1,
		GEN9_FFSC_PERCTX_PREEMPT_CTRL);

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