Commit 9af865d9 authored by Rob Herring's avatar Rob Herring
Browse files

dt-bindings: riscv: Fix CPU schema errors



Fix the errors in the RiscV CPU DT schema:

Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@1: 'timebase-frequency' is a required property
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible:0: 'riscv' is not one of ['sifive,rocket0', 'sifive,e5', 'sifive,e51', 'sifive,u54-mc', 'sifive,u54', 'sifive,u5']
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible: ['riscv'] is too short
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property

The DT spec allows for 'timebase-frequency' to be in 'cpu' or 'cpus' node
and RiscV requires it in /cpus node, so make it disallowed in cpu
nodes.

Fixes: 4fd669a8 ("dt-bindings: riscv: convert cpu binding to json-schema")
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-riscv@lists.infradead.org
Acked-by: default avatarPaul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent f437ade3
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+13 −16
Original line number Diff line number Diff line
@@ -24,7 +24,8 @@ description: |

properties:
  compatible:
    items:
    oneOf:
      - items:
          - enum:
              - sifive,rocket0
              - sifive,e5
@@ -33,6 +34,7 @@ properties:
              - sifive,u54
              - sifive,u5
          - const: riscv
      - const: riscv    # Simulator only
    description:
      Identifies that the hart uses the RISC-V instruction set
      and identifies the type of the hart.
@@ -66,12 +68,8 @@ properties:
      insensitive, letters in the riscv,isa string must be all
      lowercase to simplify parsing.

  timebase-frequency:
    type: integer
    minimum: 1
    description:
      Specifies the clock frequency of the system timer in Hz.
      This value is common to all harts on a single system image.
  # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
  timebase-frequency: false

  interrupt-controller:
    type: object
@@ -93,7 +91,6 @@ properties:

required:
  - riscv,isa
  - timebase-frequency
  - interrupt-controller

examples: