Commit 9adc8050 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
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drm/amd/display: make firmware info only load once during dc_bios create 



Currently every time DC wants to access firmware info we make a call
into VBIOS. This makes no sense as there is nothing that can change
runtime inside fw info and can cause issues when calling unstable
bios during bringup.

This change eliminate this behavior by only calling bios once for fw
info and keeping it stored as part of dc_bios.

Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarChris Park <Chris.Park@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0b226322

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

+1 −2
Original line number Diff line number Diff line
@@ -2796,8 +2796,6 @@ static const struct dc_vbios_funcs vbios_funcs = { 


	.get_device_tag = bios_parser_get_device_tag,



	.get_firmware_info = bios_parser_get_firmware_info,



	.get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,



	.get_ss_entry_number = bios_parser_get_ss_entry_number,
@@ -2922,6 +2920,7 @@ static bool bios_parser_construct( 
	dal_bios_parser_init_cmd_tbl_helper(&bp->cmd_helper, dce_version);



	bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);

	bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;



	return true;

}

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

+1 −2
Original line number Diff line number Diff line
@@ -1881,8 +1881,6 @@ static const struct dc_vbios_funcs vbios_funcs = { 


	.get_device_tag = bios_parser_get_device_tag,



	.get_firmware_info = bios_parser_get_firmware_info,



	.get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,



	.get_ss_entry_number = bios_parser_get_ss_entry_number,
@@ -1998,6 +1996,7 @@ static bool bios_parser_construct( 
	dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version);



	bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);

	bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;



	return true;

}

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

+6 −11
Original line number Diff line number Diff line
@@ -273,18 +273,12 @@ static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce) 
{

	struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug;

	struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;

	struct integrated_info info = { { { 0 } } };

	struct dc_firmware_info fw_info = { { 0 } };

	int i;



	if (bp->integrated_info)

		info = *bp->integrated_info;



	clk_mgr_dce->dentist_vco_freq_khz = info.dentist_vco_freq;

		clk_mgr_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;

	if (clk_mgr_dce->dentist_vco_freq_khz == 0) {

		bp->funcs->get_firmware_info(bp, &fw_info);

		clk_mgr_dce->dentist_vco_freq_khz =

			fw_info.smu_gpu_pll_output_freq;

		clk_mgr_dce->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;

		if (clk_mgr_dce->dentist_vco_freq_khz == 0)

			clk_mgr_dce->dentist_vco_freq_khz = 3600000;

	}
@@ -317,9 +311,10 @@ static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce) 


		/*Do not allow bad VBIOS/SBIOS to override with invalid values,

		 * check for > 100MHz*/

		if (info.disp_clk_voltage[i].max_supported_clk >= 100000)

		if (bp->integrated_info)

			if (bp->integrated_info->disp_clk_voltage[i].max_supported_clk >= 100000)

				clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz =

				info.disp_clk_voltage[i].max_supported_clk;

					bp->integrated_info->disp_clk_voltage[i].max_supported_clk;

	}



	if (!debug->disable_dfs_bypass && bp->integrated_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

+2 −4
Original line number Diff line number Diff line
@@ -246,7 +246,6 @@ void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_ 
{

	struct dc_debug_options *debug = &ctx->dc->debug;

	struct dc_bios *bp = ctx->dc_bios;

	struct dc_firmware_info fw_info = { { 0 } };



	clk_mgr->base.ctx = ctx;

	clk_mgr->pp_smu = pp_smu;
@@ -262,9 +261,8 @@ void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_ 


	if (bp->integrated_info)

		clk_mgr->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;

	if (clk_mgr->dentist_vco_freq_khz == 0) {

		bp->funcs->get_firmware_info(bp, &fw_info);

		clk_mgr->dentist_vco_freq_khz = fw_info.smu_gpu_pll_output_freq;

	if (bp->fw_info_valid && clk_mgr->dentist_vco_freq_khz == 0) {

		clk_mgr->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;

		if (clk_mgr->dentist_vco_freq_khz == 0)

			clk_mgr->dentist_vco_freq_khz = 3600000;

	}

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+2 −5
Original line number Diff line number Diff line
@@ -173,12 +173,9 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, 
		break;

	}

	if (res_pool != NULL) {

		struct dc_firmware_info fw_info = { { 0 } };



		if (dc->ctx->dc_bios->funcs->get_firmware_info(dc->ctx->dc_bios,

				&fw_info) == BP_RESULT_OK) {

		if (dc->ctx->dc_bios->fw_info_valid) {

			res_pool->ref_clocks.xtalin_clock_inKhz =

				fw_info.pll_info.crystal_frequency;

				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

			/* initialize with firmware data first, no all

			 * ASIC have DCCG SW component. FPGA or

			 * simulation need initialization of

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