Commit 9ad86ddd authored Jun 25, 2012 by Catalin Marinas Committed by Russell King Jul 09, 2012

ARM: 7436/1: Do not map the vectors page as write-through on UP systems



The vectors page has been traditionally mapped as WT on UP systems but
this creates a mismatched alias with the directly mapped RAM that is
using WB attributes. On newer processors like Cortex-A15 this has
implications on the data/instructions coherency at the point of
unification (usually L2).

This patch removes such restriction.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

parent 02df19b4

arch/arm/mm/mmu.c

+0 −6

Original line number	Diff line number	Diff line
		@@ -421,12 +421,6 @@ static void __init build_mem_type_table(void)
		cp = &cache_policies[cachepolicy];
		vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;

		/*
		* Only use write-through for non-SMP systems
		*/
		if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
		vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;

		/*
		* Enable CPU-specific coherency if supported.
		* (Only available on XSC3 at the moment.)

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