Commit 9acb961e authored by Matt Carlson's avatar Matt Carlson Committed by David S. Miller
Browse files

[TG3]: 5784 / 5764 DMA engine lockup fix 



5784 and 5764 devices lock up when the link speed is 10Mbps, the CPMU
link speed mode is enabled, and the MAC clock is running at 1.5Mhz.  The
fix is to run the MAC clock at faster speeds.

Signed-off-by: default avatarMatt Carlson <mcarlson@broadcom.com>
Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 84af67fd

drivers/net/tg3.c

+15 −0
Original line number Diff line number Diff line
@@ -6369,6 +6369,21 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) 
		val = tr32(TG3_CPMU_CTRL);

		val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);

		tw32(TG3_CPMU_CTRL, val);



		val = tr32(TG3_CPMU_LSPD_10MB_CLK);

		val &= ~CPMU_LSPD_10MB_MACCLK_MASK;

		val |= CPMU_LSPD_10MB_MACCLK_6_25;

		tw32(TG3_CPMU_LSPD_10MB_CLK, val);



		val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);

		val &= ~CPMU_LNK_AWARE_MACCLK_MASK;

		val |= CPMU_LNK_AWARE_MACCLK_6_25;

		tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);



		val = tr32(TG3_CPMU_HST_ACC);

		val &= ~CPMU_HST_ACC_MACCLK_MASK;

		val |= CPMU_HST_ACC_MACCLK_6_25;

		tw32(TG3_CPMU_HST_ACC, val);

	}



	/* This works around an issue with Athlon chipsets on

drivers/net/tg3.h

+13 −2
Original line number Diff line number Diff line
@@ -857,13 +857,24 @@ 
#define  CPMU_CTRL_LINK_IDLE_MODE	 0x00000200

#define  CPMU_CTRL_LINK_AWARE_MODE	 0x00000400

#define  CPMU_CTRL_LINK_SPEED_MODE	 0x00004000

/* 0x3604 --> 0x360c unused */

#define TG3_CPMU_LSPD_10MB_CLK		0x00003604

#define  CPMU_LSPD_10MB_MACCLK_MASK	 0x001f0000

#define  CPMU_LSPD_10MB_MACCLK_6_25	 0x00130000

/* 0x3608 --> 0x360c unused */



#define TG3_CPMU_LSPD_1000MB_CLK	0x0000360c

#define  CPMU_LSPD_1000MB_MACCLK_62_5	 0x00000000

#define  CPMU_LSPD_1000MB_MACCLK_12_5	 0x00110000

#define  CPMU_LSPD_1000MB_MACCLK_MASK	 0x001f0000

/* 0x3610 --> 0x365c unused */

#define TG3_CPMU_LNK_AWARE_PWRMD	0x00003610

#define  CPMU_LNK_AWARE_MACCLK_MASK	 0x001f0000

#define  CPMU_LNK_AWARE_MACCLK_6_25	 0x00130000

/* 0x3614 --> 0x361c unused */



#define TG3_CPMU_HST_ACC		0x0000361c

#define  CPMU_HST_ACC_MACCLK_MASK	 0x001f0000

#define  CPMU_HST_ACC_MACCLK_6_25	 0x00130000

/* 0x3620 --> 0x365c unused */



#define TG3_CPMU_MUTEX_REQ		0x0000365c

#define  CPMU_MUTEX_REQ_DRIVER		 0x00001000

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