Commit 9a715cd5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull tty/serial updates from Greg KH:
 "Here is the large tty/serial patchset for 4.13-rc1.

  A lot of tty and serial driver updates are in here, along with some
  fixups for some __get/put_user usages that were reported. Nothing
  huge, just lots of development by a number of different developers,
  full details in the shortlog.

  All of these have been in linux-next for a while"

* tag 'tty-4.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (71 commits)
  tty: serial: lpuart: add a more accurate baud rate calculation method
  tty: serial: lpuart: add earlycon support for imx7ulp
  tty: serial: lpuart: add imx7ulp support
  dt-bindings: serial: fsl-lpuart: add i.MX7ULP support
  tty: serial: lpuart: add little endian 32 bit register support
  tty: serial: lpuart: refactor lpuart32_{read|write} prototype
  tty: serial: lpuart: introduce lpuart_soc_data to represent SoC property
  serial: imx-serial - move DMA buffer configuration to DT
  serial: imx: Enable RTSD only when needed
  serial: imx: Remove unused members from imx_port struct
  serial: 8250: 8250_omap: Fix race b/w dma completion and RX timeout
  serial: 8250: Fix THRE flag usage for CAP_MINI
  tty/serial: meson_uart: update to stable bindings
  dt-bindings: serial: Add bindings for the Amlogic Meson UARTs
  serial: Delete dead code for CIR serial ports
  serial: sirf: make of_device_ids const
  serial/mpsc: switch to dma_alloc_attrs
  tty: serial: Add Actions Semi Owl UART earlycon
  dt-bindings: serial: Document Actions Semi Owl UARTs
  tty/serial: atmel: make the driver DT only
  ...
parents cbcd4f08 a6d7514b
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What:		/sys/bus/platform/drivers/aspeed-vuart/*/lpc_address
Date:		April 2017
Contact:	Jeremy Kerr <jk@ozlabs.org>
Description:	Configures which IO port the host side of the UART
		will appear on the host <-> BMC LPC bus.
Users:		OpenBMC.  Proposed changes should be mailed to
		openbmc@lists.ozlabs.org

What:		/sys/bus/platform/drivers/aspeed-vuart*/sirq
Date:		April 2017
Contact:	Jeremy Kerr <jk@ozlabs.org>
Description:	Configures which interrupt number the host side of
		the UART will appear on the host <-> BMC LPC bus.
Users:		OpenBMC.  Proposed changes should be mailed to
		openbmc@lists.ozlabs.org
+6 −0
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@@ -954,6 +954,12 @@
			must already be setup and configured. Options are not
			yet supported.

		owl,<addr>
			Start an early, polled-mode console on a serial port
			of an Actions Semi SoC, such as S500 or S900, at the
			specified address. The serial port must already be
			setup and configured. Options are not yet supported.

		smh	Use ARM semihosting calls for early console.

		s3c2410,<addr>
+3 −0
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@@ -20,6 +20,8 @@ Required properties:
	- "fsl,16550-FIFO64"
	- "fsl,ns16550"
	- "ti,da830-uart"
	- "aspeed,ast2400-vuart"
	- "aspeed,ast2500-vuart"
	- "serial" if the port type is unknown.
- reg : offset and length of the register set for the device.
- interrupts : should contain uart interrupt.
@@ -45,6 +47,7 @@ Optional properties:
  property.
- tx-threshold: Specify the TX FIFO low water indication for parts with
  programmable TX FIFO thresholds.
- resets : phandle + reset specifier pairs

Note:
* fsl,ns16550:
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Actions Semi Owl UART

Required properties:
- compatible :  "actions,s500-uart", "actions,owl-uart" for S500
                "actions,s900-uart", "actions,owl-uart" for S900
- reg        :  Offset and length of the register set for the device.
- interrupts :  Should contain UART interrupt.


Example:

		uart3: serial@b0126000 {
			compatible = "actions,s500-uart", "actions,owl-uart";
			reg = <0xb0126000 0x1000>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		};
+38 −0
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Amlogic Meson SoC UART Serial Interface
=======================================

The Amlogic Meson SoC UART Serial Interface is present on a large range
of SoCs, and can be present either in the "Always-On" power domain or the
"Everything-Else" power domain.

The particularity of the "Always-On" Serial Interface is that the hardware
is active since power-on and does not need any clock gating and is usable
as very early serial console.

Required properties:
- compatible : compatible: value should be different for each SoC family as :
	- Meson6 : "amlogic,meson6-uart"
	- Meson8 : "amlogic,meson8-uart"
	- Meson8b : "amlogic,meson8b-uart"
	- GX (GXBB, GXL, GXM) : "amlogic,meson-gx-uart"
	eventually followed by : "amlogic,meson-ao-uart" if this UART interface
	is in the "Always-On" power domain.
- reg : offset and length of the register set for the device.
- interrupts : identifier to the device interrupt
- clocks : a list of phandle + clock-specifier pairs, one for each
	   entry in clock names.
- clocks-names :
   * "xtal" for external xtal clock identifier
   * "pclk" for the bus core clock, either the clk81 clock or the gate clock
   * "baud" for the source of the baudrate generator, can be either the xtal
	or the pclk.

e.g.
uart_A: serial@84c0 {
	compatible = "amlogic,meson-gx-uart";
	reg = <0x0 0x84c0 0x0 0x14>;
	interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
	/* Use xtal as baud rate clock source */
	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
	clock-names = "xtal", "pclk", "baud";
};
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