Commit 99efd1c9 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Eliminate skl_check_pipe_max_pixel_rate() 



The normal cdclk handling now takes care of making sure the
plane's pixel rate doesn't exceed the spec appointed percentage
of the cdclk frequency. Thus we can nuke
skl_check_pipe_max_pixel_rate().

Reviewed-by: default avatarJuha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191015193035.25982-6-ville.syrjala@linux.intel.com
parent bb6ae9e6

drivers/gpu/drm/i915/display/intel_display.c

+0 −2
Original line number Diff line number Diff line
@@ -12121,8 +12121,6 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, 
	if (INTEL_GEN(dev_priv) >= 9) {

		if (mode_changed || crtc_state->update_pipe)

			ret = skl_update_scaler_crtc(crtc_state);

		if (!ret)

			ret = skl_check_pipe_max_pixel_rate(crtc, crtc_state);

		if (!ret)

			ret = intel_atomic_setup_scalers(dev_priv, crtc,

							 crtc_state);

drivers/gpu/drm/i915/intel_pm.c

+0 −87
Original line number Diff line number Diff line
@@ -4097,93 +4097,6 @@ skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state, 
	return mul_fixed16(downscale_w, downscale_h);

}



static uint_fixed_16_16_t

skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)

{

	uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1);



	if (!crtc_state->base.enable)

		return pipe_downscale;



	if (crtc_state->pch_pfit.enabled) {

		u32 src_w, src_h, dst_w, dst_h;

		u32 pfit_size = crtc_state->pch_pfit.size;

		uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;

		uint_fixed_16_16_t downscale_h, downscale_w;



		src_w = crtc_state->pipe_src_w;

		src_h = crtc_state->pipe_src_h;

		dst_w = pfit_size >> 16;

		dst_h = pfit_size & 0xffff;



		if (!dst_w || !dst_h)

			return pipe_downscale;



		fp_w_ratio = div_fixed16(src_w, dst_w);

		fp_h_ratio = div_fixed16(src_h, dst_h);

		downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));

		downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));



		pipe_downscale = mul_fixed16(downscale_w, downscale_h);

	}



	return pipe_downscale;

}



int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,

				  struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);

	struct drm_atomic_state *state = crtc_state->base.state;

	const struct intel_plane_state *plane_state;

	struct intel_plane *plane;

	int crtc_clock, dotclk;

	u32 pipe_max_pixel_rate;

	uint_fixed_16_16_t pipe_downscale;

	uint_fixed_16_16_t max_downscale = u32_to_fixed16(1);



	if (!crtc_state->base.enable)

		return 0;



	intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {

		uint_fixed_16_16_t plane_downscale;

		uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8);

		int bpp;



		if (!intel_wm_plane_visible(crtc_state, plane_state))

			continue;



		if (WARN_ON(!plane_state->base.fb))

			return -EINVAL;



		plane_downscale = skl_plane_downscale_amount(crtc_state, plane_state);

		bpp = plane_state->base.fb->format->cpp[0] * 8;

		if (bpp == 64)

			plane_downscale = mul_fixed16(plane_downscale,

						      fp_9_div_8);



		max_downscale = max_fixed16(plane_downscale, max_downscale);

	}

	pipe_downscale = skl_pipe_downscale_amount(crtc_state);



	pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);



	crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;

	dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;



	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)

		dotclk *= 2;



	pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);



	if (pipe_max_pixel_rate < crtc_clock) {

		DRM_DEBUG_KMS("Max supported pixel clock with scaling exceeded\n");

		return -EINVAL;

	}



	return 0;

}



static u64

skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,

			     const struct intel_plane_state *plane_state,

drivers/gpu/drm/i915/intel_pm.h

+0 −2
Original line number Diff line number Diff line
@@ -64,8 +64,6 @@ void skl_write_plane_wm(struct intel_plane *plane, 
void skl_write_cursor_wm(struct intel_plane *plane,

			 const struct intel_crtc_state *crtc_state);

bool ilk_disable_lp_wm(struct drm_device *dev);

int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,

				  struct intel_crtc_state *cstate);

void intel_init_ipc(struct drm_i915_private *dev_priv);

void intel_enable_ipc(struct drm_i915_private *dev_priv);

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