Commit 99e7938d authored by Rajendra Nayak's avatar Rajendra Nayak Committed by Paul Walmsley
Browse files

ARM: OMAP3: clock: Add 3xxx data using common struct clk 



The patch is the output from a python script which converts
from the old OMAP clk format to COMMON clk format using a
JSON parser in between which was developed by Paul Walmsley.

Signed-off-by: default avatarRajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: AM3517/05: dropped bogus hsotgusb "ick" and "fck"
 clkdev aliases; added hsotgusb_fck alias; added emac_ick and emac_fck
 aliases; replace omap2_init_clksel_parent() with
 omap2_clksel_find_parent_index(); reflow macros and parent name
 lists; add clkdm_name argument to DEFINE_STRUCT_CLK_HW_OMAP macros]
Signed-off-by: default avatarMike Turquette <mturquette@ti.com>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent b4c63295

arch/arm/mach-omap2/cclock3xxx_data.c

0 → 100644
+3595 −0

File added.

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arch/arm/mach-omap2/cm-regbits-34xx.h

+31 −0
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ 
/* CM_CLKSEL1_PLL_IVA2 */

#define OMAP3430_IVA2_CLK_SRC_SHIFT			19

#define OMAP3430_IVA2_CLK_SRC_MASK			(0x7 << 19)

#define OMAP3430_IVA2_CLK_SRC_WIDTH			3

#define OMAP3430_IVA2_DPLL_MULT_SHIFT			8

#define OMAP3430_IVA2_DPLL_MULT_MASK			(0x7ff << 8)

#define OMAP3430_IVA2_DPLL_DIV_SHIFT			0
@@ -89,6 +90,7 @@ 
/* CM_CLKSEL2_PLL_IVA2 */

#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT		0

#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK		(0x1f << 0)

#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH		5



/* CM_CLKSTCTRL_IVA2 */

#define OMAP3430_CLKTRCTRL_IVA2_SHIFT			0
@@ -118,6 +120,7 @@ 
/* CM_IDLEST_PLL_MPU */

#define OMAP3430_ST_MPU_CLK_SHIFT			0

#define OMAP3430_ST_MPU_CLK_MASK			(1 << 0)

#define OMAP3430_ST_MPU_CLK_WIDTH			1



/* CM_AUTOIDLE_PLL_MPU */

#define OMAP3430_AUTO_MPU_DPLL_SHIFT			0
@@ -126,6 +129,7 @@ 
/* CM_CLKSEL1_PLL_MPU */

#define OMAP3430_MPU_CLK_SRC_SHIFT			19

#define OMAP3430_MPU_CLK_SRC_MASK			(0x7 << 19)

#define OMAP3430_MPU_CLK_SRC_WIDTH			3

#define OMAP3430_MPU_DPLL_MULT_SHIFT			8

#define OMAP3430_MPU_DPLL_MULT_MASK			(0x7ff << 8)

#define OMAP3430_MPU_DPLL_DIV_SHIFT			0
@@ -134,6 +138,7 @@ 
/* CM_CLKSEL2_PLL_MPU */

#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT		0

#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK		(0x1f << 0)

#define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH		5



/* CM_CLKSTCTRL_MPU */

#define OMAP3430_CLKTRCTRL_MPU_SHIFT			0
@@ -345,10 +350,13 @@ 
#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK		(0x3 << 4)

#define OMAP3430_CLKSEL_L4_SHIFT			2

#define OMAP3430_CLKSEL_L4_MASK				(0x3 << 2)

#define OMAP3430_CLKSEL_L4_WIDTH			2

#define OMAP3430_CLKSEL_L3_SHIFT			0

#define OMAP3430_CLKSEL_L3_MASK				(0x3 << 0)

#define OMAP3430_CLKSEL_L3_WIDTH			2

#define OMAP3630_CLKSEL_96M_SHIFT			12

#define OMAP3630_CLKSEL_96M_MASK			(0x3 << 12)

#define OMAP3630_CLKSEL_96M_WIDTH			2



/* CM_CLKSTCTRL_CORE */

#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT			4
@@ -452,6 +460,7 @@ 
#define OMAP3430ES2_CLKSEL_USIMOCP_MASK			(0xf << 3)

#define OMAP3430_CLKSEL_RM_SHIFT			1

#define OMAP3430_CLKSEL_RM_MASK				(0x3 << 1)

#define OMAP3430_CLKSEL_RM_WIDTH			2

#define OMAP3430_CLKSEL_GPT1_SHIFT			0

#define OMAP3430_CLKSEL_GPT1_MASK			(1 << 0)
@@ -520,14 +529,17 @@ 
/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */

#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT		27

#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK		(0x1f << 27)

#define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH		5

#define OMAP3430_CORE_DPLL_MULT_SHIFT			16

#define OMAP3430_CORE_DPLL_MULT_MASK			(0x7ff << 16)

#define OMAP3430_CORE_DPLL_DIV_SHIFT			8

#define OMAP3430_CORE_DPLL_DIV_MASK			(0x7f << 8)

#define OMAP3430_SOURCE_96M_SHIFT			6

#define OMAP3430_SOURCE_96M_MASK			(1 << 6)

#define OMAP3430_SOURCE_96M_WIDTH			1

#define OMAP3430_SOURCE_54M_SHIFT			5

#define OMAP3430_SOURCE_54M_MASK			(1 << 5)

#define OMAP3430_SOURCE_54M_WIDTH			1

#define OMAP3430_SOURCE_48M_SHIFT			3

#define OMAP3430_SOURCE_48M_MASK			(1 << 3)
@@ -545,7 +557,9 @@ 
/* CM_CLKSEL3_PLL */

#define OMAP3430_DIV_96M_SHIFT				0

#define OMAP3430_DIV_96M_MASK				(0x1f << 0)

#define OMAP3430_DIV_96M_WIDTH				5

#define OMAP3630_DIV_96M_MASK				(0x3f << 0)

#define OMAP3630_DIV_96M_WIDTH				6



/* CM_CLKSEL4_PLL */

#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT		8
@@ -556,12 +570,14 @@ 
/* CM_CLKSEL5_PLL */

#define OMAP3430ES2_DIV_120M_SHIFT			0

#define OMAP3430ES2_DIV_120M_MASK			(0x1f << 0)

#define OMAP3430ES2_DIV_120M_WIDTH			5



/* CM_CLKOUT_CTRL */

#define OMAP3430_CLKOUT2_EN_SHIFT			7

#define OMAP3430_CLKOUT2_EN_MASK			(1 << 7)

#define OMAP3430_CLKOUT2_DIV_SHIFT			3

#define OMAP3430_CLKOUT2_DIV_MASK			(0x7 << 3)

#define OMAP3430_CLKOUT2_DIV_WIDTH			3

#define OMAP3430_CLKOUT2SOURCE_SHIFT			0

#define OMAP3430_CLKOUT2SOURCE_MASK			(0x3 << 0)
@@ -592,10 +608,14 @@ 
/* CM_CLKSEL_DSS */

#define OMAP3430_CLKSEL_TV_SHIFT			8

#define OMAP3430_CLKSEL_TV_MASK				(0x1f << 8)

#define OMAP3430_CLKSEL_TV_WIDTH			5

#define OMAP3630_CLKSEL_TV_MASK				(0x3f << 8)

#define OMAP3630_CLKSEL_TV_WIDTH			6

#define OMAP3430_CLKSEL_DSS1_SHIFT			0

#define OMAP3430_CLKSEL_DSS1_MASK			(0x1f << 0)

#define OMAP3430_CLKSEL_DSS1_WIDTH			5

#define OMAP3630_CLKSEL_DSS1_MASK			(0x3f << 0)

#define OMAP3630_CLKSEL_DSS1_WIDTH			6



/* CM_SLEEPDEP_DSS specific bits */
@@ -623,7 +643,9 @@ 
/* CM_CLKSEL_CAM */

#define OMAP3430_CLKSEL_CAM_SHIFT			0

#define OMAP3430_CLKSEL_CAM_MASK			(0x1f << 0)

#define OMAP3430_CLKSEL_CAM_WIDTH			5

#define OMAP3630_CLKSEL_CAM_MASK			(0x3f << 0)

#define OMAP3630_CLKSEL_CAM_WIDTH			6



/* CM_SLEEPDEP_CAM specific bits */
@@ -721,21 +743,30 @@ 
/* CM_CLKSEL1_EMU */

#define OMAP3430_DIV_DPLL4_SHIFT			24

#define OMAP3430_DIV_DPLL4_MASK				(0x1f << 24)

#define OMAP3430_DIV_DPLL4_WIDTH			5

#define OMAP3630_DIV_DPLL4_MASK				(0x3f << 24)

#define OMAP3630_DIV_DPLL4_WIDTH			6

#define OMAP3430_DIV_DPLL3_SHIFT			16

#define OMAP3430_DIV_DPLL3_MASK				(0x1f << 16)

#define OMAP3430_DIV_DPLL3_WIDTH			5

#define OMAP3430_CLKSEL_TRACECLK_SHIFT			11

#define OMAP3430_CLKSEL_TRACECLK_MASK			(0x7 << 11)

#define OMAP3430_CLKSEL_TRACECLK_WIDTH			3

#define OMAP3430_CLKSEL_PCLK_SHIFT			8

#define OMAP3430_CLKSEL_PCLK_MASK			(0x7 << 8)

#define OMAP3430_CLKSEL_PCLK_WIDTH			3

#define OMAP3430_CLKSEL_PCLKX2_SHIFT			6

#define OMAP3430_CLKSEL_PCLKX2_MASK			(0x3 << 6)

#define OMAP3430_CLKSEL_PCLKX2_WIDTH			2

#define OMAP3430_CLKSEL_ATCLK_SHIFT			4

#define OMAP3430_CLKSEL_ATCLK_MASK			(0x3 << 4)

#define OMAP3430_CLKSEL_ATCLK_WIDTH			2

#define OMAP3430_TRACE_MUX_CTRL_SHIFT			2

#define OMAP3430_TRACE_MUX_CTRL_MASK			(0x3 << 2)

#define OMAP3430_TRACE_MUX_CTRL_WIDTH			2

#define OMAP3430_MUX_CTRL_SHIFT				0

#define OMAP3430_MUX_CTRL_MASK				(0x3 << 0)

#define OMAP3430_MUX_CTRL_WIDTH				2



/* CM_CLKSTCTRL_EMU */

#define OMAP3430_CLKTRCTRL_EMU_SHIFT			0

arch/arm/mach-omap2/cm2xxx_3xxx.h

+1 −0
Original line number Diff line number Diff line
@@ -108,6 +108,7 @@ extern void omap2xxx_cm_apll96_disable(void); 
/* CM_CLKSEL_GFX */

#define OMAP_CLKSEL_GFX_SHIFT				0

#define OMAP_CLKSEL_GFX_MASK				(0x7 << 0)

#define OMAP_CLKSEL_GFX_WIDTH				3



/* CM_ICLKEN_GFX */

#define OMAP_EN_GFX_SHIFT				0

arch/arm/mach-omap2/prm-regbits-34xx.h

+1 −0
Original line number Diff line number Diff line
@@ -384,6 +384,7 @@ 
/* PRM_CLKSEL */

#define OMAP3430_SYS_CLKIN_SEL_SHIFT			0

#define OMAP3430_SYS_CLKIN_SEL_MASK			(0x7 << 0)

#define OMAP3430_SYS_CLKIN_SEL_WIDTH			3



/* PRM_CLKOUT_CTRL */

#define OMAP3430_CLKOUT_EN_MASK				(1 << 7)

arch/arm/mach-omap2/prm2xxx_3xxx.h

+1 −0
Original line number Diff line number Diff line
@@ -152,6 +152,7 @@ extern int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm); 
/* Named PRCM_CLKSRC_CTRL on the 24XX */

#define OMAP_SYSCLKDIV_SHIFT				6

#define OMAP_SYSCLKDIV_MASK				(0x3 << 6)

#define OMAP_SYSCLKDIV_WIDTH				2

#define OMAP_AUTOEXTCLKMODE_SHIFT			3

#define OMAP_AUTOEXTCLKMODE_MASK			(0x3 << 3)

#define OMAP_SYSCLKSEL_SHIFT				0

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