Commit 99e1dfb7 authored Jul 13, 2015 by Aravind Gopalakrishnan Committed by Borislav Petkov Jul 14, 2015

EDAC, mce_amd: Don't emit 'CE' for Deferred error



Currently, when decoding an MCE, we display 'CE' for a Deferred error, like
this:

[Hardware Error]: CPU:0 (15:2:0) MC4_STATUS[Over|CE|MiscV|-|AddrV|Deferred|-|UECC]: 0xdc04b00095080813

When the 'UC' bit in the MCx_STATUS register is clear, the error status
is either a Corrected error or Deferred error as determined by the
'Deferred' bit. So do not print 'CE' on a deferred error.

Refer to AMD Error Scope Hierarchy table in a newer BKDG (example:
49125_15h_Models_30h-3Fh_BKDG.pdf, section "RAS Features").

Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1436788382-6463-1-git-send-email-aravind.gopalakrishnan@amd.com


Signed-off-by: Borislav Petkov <bp@suse.de>

parent ca12bb14

drivers/edac/mce_amd.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -763,7 +763,8 @@ int amd_decode_mce(struct notifier_block nb, unsigned long val, void data)
		c->x86, c->x86_model, c->x86_mask,
		m->bank,
		((m->status & MCI_STATUS_OVER) ? "Over" : "-"),
		((m->status & MCI_STATUS_UC) ? "UE" : "CE"),
		((m->status & MCI_STATUS_UC) ? "UE" :
		(m->status & MCI_STATUS_DEFERRED) ? "-" : "CE"),
		((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"),
		((m->status & MCI_STATUS_PCC) ? "PCC" : "-"),
		((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"));

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