Commit 99dd8713 authored by Cliff Wickman's avatar Cliff Wickman Committed by Ingo Molnar
Browse files

x86, SGI UV: hardcode the TLB flush interrupt system vector 



The UV TLB shootdown mechanism needs a system interrupt vector.

Its vector had been hardcoded as 200, but needs to moved to the reserved
system vector range so that it does not collide with some device vector.

This is still temporary until dynamic system IRQ allocation is provided.
But it will be needed when real UV hardware becomes available and runs 2.6.27.

Signed-off-by: default avatarCliff Wickman <cpw@sgi.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 80c5e73d

arch/x86/kernel/tlb_uv.c

+2 −1
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include <asm/genapic.h>

#include <asm/idle.h>

#include <asm/tsc.h>

#include <asm/irq_vectors.h>



#include <mach_apic.h>
@@ -783,7 +784,7 @@ static int __init uv_bau_init(void) 
		uv_init_blade(blade, node, cur_cpu);

		cur_cpu += uv_blade_nr_possible_cpus(blade);

	}

	set_intr_gate(UV_BAU_MESSAGE, uv_bau_message_intr1);

	alloc_intr_gate(UV_BAU_MESSAGE, uv_bau_message_intr1);

	uv_enable_timeouts();



	return 0;

include/asm-x86/irq_vectors.h

+1 −0
Original line number Diff line number Diff line
@@ -76,6 +76,7 @@ 
#define CALL_FUNCTION_SINGLE_VECTOR	0xfb

#define THERMAL_APIC_VECTOR		0xfa

#define THRESHOLD_APIC_VECTOR		0xf9

#define UV_BAU_MESSAGE			0xf8

#define INVALIDATE_TLB_VECTOR_END	0xf7

#define INVALIDATE_TLB_VECTOR_START	0xf0	/* f0-f7 used for TLB flush */

include/asm-x86/uv/uv_bau.h

+0 −5
Original line number Diff line number Diff line
@@ -40,11 +40,6 @@ 
#define UV_ACTIVATION_DESCRIPTOR_SIZE	32

#define UV_DISTRIBUTION_SIZE		256

#define UV_SW_ACK_NPENDING		8

#define UV_BAU_MESSAGE			200

/*

 * Messaging irq; see irq_64.h and include/asm-x86/hw_irq_64.h

 * To be dynamically allocated in the future

 */

#define UV_NET_ENDPOINT_INTD		0x38

#define UV_DESC_BASE_PNODE_SHIFT	49

#define UV_PAYLOADQ_PNODE_SHIFT		49

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