Commit 999dcbe2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq updates from Thomas Gleixner:
 "The irq departement proudly presents:

   - A rework of the core infrastructure to optimally spread interrupt
     for multiqueue devices. The first version was a bit naive and
     failed to take thread siblings and other details into account.
     Developed in cooperation with Christoph and Keith.

   - Proper delegation of softirqs to ksoftirqd, so if ksoftirqd is
     active then no further softirq processsing on interrupt return
     happens. Otherwise we try to delegate and still run another batch
     of network packets in the irq return path, which then tries to
     delegate to ksoftirqd .....

   - A proper machine parseable sysfs based alternative for
     /proc/interrupts.

   - ACPI support for the GICV3-ITS and ARM interrupt remapping

   - Two new irq chips from the ARM SoC zoo: STM32-EXTI and MVEBU-PIC

   - A new irq chip for the JCore (SuperH)

   - The usual pile of small fixlets in core and irqchip drivers"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (42 commits)
  softirq: Let ksoftirqd do its job
  genirq: Make function __irq_do_set_handler() static
  ARM/dts: Add EXTI controller node to stm32f429
  ARM/STM32: Select external interrupts controller
  drivers/irqchip: Add STM32 external interrupts support
  Documentation/dt-bindings: Document STM32 EXTI controller bindings
  irqchip/mips-gic: Use for_each_set_bit to iterate over local IRQs
  pci/msi: Retrieve affinity for a vector
  genirq/affinity: Remove old irq spread infrastructure
  genirq/msi: Switch to new irq spreading infrastructure
  genirq/affinity: Provide smarter irq spreading infrastructure
  genirq/msi: Add cpumask allocation to alloc_msi_entry
  genirq: Expose interrupt information through sysfs
  irqchip/gicv3-its: Use MADT ITS subtable to do PCI/MSI domain initialization
  irqchip/gicv3-its: Factor out PCI-MSI part that might be reused for ACPI
  irqchip/gicv3-its: Probe ITS in the ACPI way
  irqchip/gicv3-its: Refactor ITS DT init code to prepare for ACPI
  irqchip/gicv3-its: Cleanup for ITS domain initialization
  PCI/MSI: Setup MSI domain on a per-device basis using IORT ACPI table
  ACPI: Add new IORT functions to support MSI domain handling
  ...
parents 5e1b834b 4cd13c21

Documentation/ABI/testing/sysfs-kernel-irq

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What:		/sys/kernel/irq

Date:		September 2016

KernelVersion:	4.9

Contact:	Craig Gallek <kraig@google.com>

Description:	Directory containing information about the system's IRQs.

		Specifically, data from the associated struct irq_desc.

		The information here is similar to that in /proc/interrupts

		but in a more machine-friendly format.  This directory contains

		one subdirectory for each Linux IRQ number.



What:		/sys/kernel/irq/<irq>/actions

Date:		September 2016

KernelVersion:	4.9

Contact:	Craig Gallek <kraig@google.com>

Description:	The IRQ action chain.  A comma-separated list of zero or more

		device names associated with this interrupt.



What:		/sys/kernel/irq/<irq>/chip_name

Date:		September 2016

KernelVersion:	4.9

Contact:	Craig Gallek <kraig@google.com>

Description:	Human-readable chip name supplied by the associated device

		driver.



What:		/sys/kernel/irq/<irq>/hwirq

Date:		September 2016

KernelVersion:	4.9

Contact:	Craig Gallek <kraig@google.com>

Description:	When interrupt translation domains are used, this file contains

		the underlying hardware IRQ number used for this Linux IRQ.



What:		/sys/kernel/irq/<irq>/name

Date:		September 2016

KernelVersion:	4.9

Contact:	Craig Gallek <kraig@google.com>

Description:	Human-readable flow handler name as defined by the irq chip

		driver.



What:		/sys/kernel/irq/<irq>/per_cpu_count

Date:		September 2016

KernelVersion:	4.9

Contact:	Craig Gallek <kraig@google.com>

Description:	The number of times the interrupt has fired since boot.  This

		is a comma-separated list of counters; one per CPU in CPU id

		order.  NOTE: This file consistently shows counters for all

		CPU ids.  This differs from the behavior of /proc/interrupts

		which only shows counters for online CPUs.



What:		/sys/kernel/irq/<irq>/type

Date:		September 2016

KernelVersion:	4.9

Contact:	Craig Gallek <kraig@google.com>

Description:	The type of the interrupt.  Either the string 'level' or 'edge'.

Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt

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J-Core Advanced Interrupt Controller



Required properties:



- compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic

  with 8 interrupt lines with programmable priorities, or "jcore,aic2" for

  the "aic2" core with 64 interrupts.



- reg: Memory region(s) for configuration. For SMP, there should be one

  region per cpu, indexed by the sequential, zero-based hardware cpu

  number.



- interrupt-controller: Identifies the node as an interrupt controller



- #interrupt-cells: Specifies the number of cells needed to encode an

  interrupt source. The value shall be 1.





Example:



aic: interrupt-controller@200 {

	compatible = "jcore,aic2";

	reg = < 0x200 0x30 0x500 0x30 >;

	interrupt-controller;

	#interrupt-cells = <1>;

};

Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.txt

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Marvell Armada 7K/8K PIC Interrupt controller

---------------------------------------------



This is the Device Tree binding for the PIC, a secondary interrupt

controller available on the Marvell Armada 7K/8K ARM64 SoCs, and

typically connected to the GIC as the primary interrupt controller.



Required properties:

- compatible: should be "marvell,armada-8k-pic"

- interrupt-controller: identifies the node as an interrupt controller

- #interrupt-cells: the number of cells to define interrupts on this

  controller. Should be 1

- reg: the register area for the PIC interrupt controller

- interrupts: the interrupt to the primary interrupt controller,

  typically the GIC



Example:



	pic: interrupt-controller@3f0100 {

		compatible = "marvell,armada-8k-pic";

		reg = <0x3f0100 0x10>;

		#interrupt-cells = <1>;

		interrupt-controller;

		interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;

	};

Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt

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@@ -31,7 +31,7 @@ Required properties: 
Example:



	odmi: odmi@300000 {

		compatible = "marvell,ap806-odm-controller",

		compatible = "marvell,ap806-odmi-controller",

			     "marvell,odmi-controller";

		interrupt-controller;

		msi-controller;

Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt

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STM32 External Interrupt Controller



Required properties:



- compatible: Should be "st,stm32-exti"

- reg: Specifies base physical address and size of the registers

- interrupt-controller: Indentifies the node as an interrupt controller

- #interrupt-cells: Specifies the number of cells to encode an interrupt

  specifier, shall be 2

- interrupts: interrupts references to primary interrupt controller



Example:



exti: interrupt-controller@40013c00 {

	compatible = "st,stm32-exti";

	interrupt-controller;

	#interrupt-cells = <2>;

	reg = <0x40013C00 0x400>;

	interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;

};

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