x86/cpu: Relocate sync_core() to sync_core.h (9998a983) · Commits · 戴 / test

arch/x86/include/asm/processor.h

+0 −64

Original line number	Diff line number	Diff line
		@@ -678,70 +678,6 @@ static inline unsigned int cpuid_edx(unsigned int op)
		return edx;
		}

		/*
		* This function forces the icache and prefetched instruction stream to
		* catch up with reality in two very specific cases:
		*
		* a) Text was modified using one virtual address and is about to be executed
		* from the same physical page at a different virtual address.
		*
		* b) Text was modified on a different CPU, may subsequently be
		* executed on this CPU, and you want to make sure the new version
		* gets executed. This generally means you're calling this in a IPI.
		*
		* If you're calling this for a different reason, you're probably doing
		* it wrong.
		*/
		static inline void sync_core(void)
		{
		/*
		* There are quite a few ways to do this. IRET-to-self is nice
		* because it works on every CPU, at any CPL (so it's compatible
		* with paravirtualization), and it never exits to a hypervisor.
		* The only down sides are that it's a bit slow (it seems to be
		* a bit more than 2x slower than the fastest options) and that
		* it unmasks NMIs. The "push %cs" is needed because, in
		* paravirtual environments, __KERNEL_CS may not be a valid CS
		* value when we do IRET directly.
		*
		* In case NMI unmasking or performance ever becomes a problem,
		* the next best option appears to be MOV-to-CR2 and an
		* unconditional jump. That sequence also works on all CPUs,
		* but it will fault at CPL3 (i.e. Xen PV).
		*
		* CPUID is the conventional way, but it's nasty: it doesn't
		* exist on some 486-like CPUs, and it usually exits to a
		* hypervisor.
		*
		* Like all of Linux's memory ordering operations, this is a
		* compiler barrier as well.
		*/
		#ifdef CONFIG_X86_32
		asm volatile (
		"pushfl\n\t"
		"pushl %%cs\n\t"
		"pushl $1f\n\t"
		"iret\n\t"
		"1:"
		: ASM_CALL_CONSTRAINT : : "memory");
		#else
		unsigned int tmp;

		asm volatile (
		"mov %%ss, %0\n\t"
		"pushq %q0\n\t"
		"pushq %%rsp\n\t"
		"addq $8, (%%rsp)\n\t"
		"pushfq\n\t"
		"mov %%cs, %0\n\t"
		"pushq %q0\n\t"
		"pushq $1f\n\t"
		"iretq\n\t"
		"1:"
		: "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory");
		#endif
		}

		extern void select_idle_routine(const struct cpuinfo_x86 *c);
		extern void amd_e400_c1e_apic_setup(void);

arch/x86/include/asm/sync_core.h

+64 −0

Original line number	Diff line number	Diff line
		@@ -6,6 +6,70 @@
		#include <asm/processor.h>
		#include <asm/cpufeature.h>

		/*
		* This function forces the icache and prefetched instruction stream to
		* catch up with reality in two very specific cases:
		*
		* a) Text was modified using one virtual address and is about to be executed
		* from the same physical page at a different virtual address.
		*
		* b) Text was modified on a different CPU, may subsequently be
		* executed on this CPU, and you want to make sure the new version
		* gets executed. This generally means you're calling this in a IPI.
		*
		* If you're calling this for a different reason, you're probably doing
		* it wrong.
		*/
		static inline void sync_core(void)
		{
		/*
		* There are quite a few ways to do this. IRET-to-self is nice
		* because it works on every CPU, at any CPL (so it's compatible
		* with paravirtualization), and it never exits to a hypervisor.
		* The only down sides are that it's a bit slow (it seems to be
		* a bit more than 2x slower than the fastest options) and that
		* it unmasks NMIs. The "push %cs" is needed because, in
		* paravirtual environments, __KERNEL_CS may not be a valid CS
		* value when we do IRET directly.
		*
		* In case NMI unmasking or performance ever becomes a problem,
		* the next best option appears to be MOV-to-CR2 and an
		* unconditional jump. That sequence also works on all CPUs,
		* but it will fault at CPL3 (i.e. Xen PV).
		*
		* CPUID is the conventional way, but it's nasty: it doesn't
		* exist on some 486-like CPUs, and it usually exits to a
		* hypervisor.
		*
		* Like all of Linux's memory ordering operations, this is a
		* compiler barrier as well.
		*/
		#ifdef CONFIG_X86_32
		asm volatile (
		"pushfl\n\t"
		"pushl %%cs\n\t"
		"pushl $1f\n\t"
		"iret\n\t"
		"1:"
		: ASM_CALL_CONSTRAINT : : "memory");
		#else
		unsigned int tmp;

		asm volatile (
		"mov %%ss, %0\n\t"
		"pushq %q0\n\t"
		"pushq %%rsp\n\t"
		"addq $8, (%%rsp)\n\t"
		"pushfq\n\t"
		"mov %%cs, %0\n\t"
		"pushq %q0\n\t"
		"pushq $1f\n\t"
		"iretq\n\t"
		"1:"
		: "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory");
		#endif
		}

		/*
		* Ensure that a core serializing instruction is issued before returning
		* to user-mode. x86 implements return to user-space through sysexit,

arch/x86/kernel/alternative.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -15,6 +15,7 @@
		#include <linux/kprobes.h>
		#include <linux/mmu_context.h>
		#include <linux/bsearch.h>
		#include <linux/sync_core.h>
		#include <asm/text-patching.h>
		#include <asm/alternative.h>
		#include <asm/sections.h>

arch/x86/kernel/cpu/mce/core.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -42,6 +42,7 @@
		#include <linux/export.h>
		#include <linux/jump_label.h>
		#include <linux/set_memory.h>
		#include <linux/sync_core.h>
		#include <linux/task_work.h>
		#include <linux/hardirq.h>

drivers/misc/sgi-gru/grufault.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -20,6 +20,7 @@
		#include <linux/io.h>
		#include <linux/uaccess.h>
		#include <linux/security.h>
		#include <linux/sync_core.h>
		#include <linux/prefetch.h>
		#include "gru.h"
		#include "grutables.h"

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