Commit 999079c8 authored by Serge Semin's avatar Serge Semin Committed by Thomas Bogendoerfer
Browse files

mips: Add CONFIG/CONFIG6/Cause reg fields macro 



There are bit fields which persist in the MIPS CONFIG and CONFIG6
registers, but haven't been described in the generic mipsregs.h
header so far. In particular, the generic CONFIG bitfields are
BE - endian mode, BM - burst mode, SB - SimpleBE, OCP interface mode
indicator, UDI - user-defined "CorExtend" instructions, DSP - data
scratch pad RAM present, ISP - instruction scratch pad RAM present,
etc. The core-specific CONFIG6 bitfields are JRCD - jump register
cache prediction disable, R6 - MIPSr6 extensions enable, IFUPerfCtl -
IFU performance control, SPCD - sleep state performance counter, DLSB -
disable load/store bonding. A new exception code reported in the
ExcCode field of the Cause register: 30 - Parity/ECC error exception
happened on either fetch, load or cache refill. Lets add them to the
mipsregs.h header to be used in future platform code, which have them
utilized.

Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 742318ad

arch/mips/include/asm/mipsregs.h

+19 −0
Original line number Diff line number Diff line
@@ -468,6 +468,7 @@ 
#define EXCCODE_THREAD		25	/* Thread exceptions (MT) */

#define EXCCODE_DSPDIS		26	/* DSP disabled exception */

#define EXCCODE_GE		27	/* Virtualized guest exception (VZ) */

#define EXCCODE_CACHEERR	30	/* Parity/ECC occured on a core */



/* Implementation specific trap codes used by MIPS cores */

#define MIPS_EXCCODE_TLBPAR	16	/* TLB parity error exception */
@@ -563,9 +564,17 @@ 
#define MIPS_CONF_MT_FTLB	(_ULCAST_(4) <<  7)

#define MIPS_CONF_AR		(_ULCAST_(7) << 10)

#define MIPS_CONF_AT		(_ULCAST_(3) << 13)

#define MIPS_CONF_BE		(_ULCAST_(1) << 15)

#define MIPS_CONF_BM		(_ULCAST_(1) << 16)

#define MIPS_CONF_MM		(_ULCAST_(3) << 17)

#define MIPS_CONF_MM_SYSAD	(_ULCAST_(1) << 17)

#define MIPS_CONF_MM_FULL	(_ULCAST_(2) << 17)

#define MIPS_CONF_SB		(_ULCAST_(1) << 21)

#define MIPS_CONF_UDI		(_ULCAST_(1) << 22)

#define MIPS_CONF_DSP		(_ULCAST_(1) << 23)

#define MIPS_CONF_ISP		(_ULCAST_(1) << 24)

#define MIPS_CONF_KU		(_ULCAST_(3) << 25)

#define MIPS_CONF_K23		(_ULCAST_(3) << 28)

#define MIPS_CONF_M		(_ULCAST_(1) << 31)



/*
@@ -677,9 +686,19 @@ 
#define MIPS_CONF5_CV		(_ULCAST_(1) << 29)

#define MIPS_CONF5_K		(_ULCAST_(1) << 30)



/* Jump register cache prediction disable */

#define MIPS_CONF6_JRCD		(_ULCAST_(1) << 0)

/* MIPSr6 extensions enable */

#define MIPS_CONF6_R6		(_ULCAST_(1) << 2)

/* IFU Performance Control */

#define MIPS_CONF6_IFUPERFCTL	(_ULCAST_(3) << 10)

#define MIPS_CONF6_SYND		(_ULCAST_(1) << 13)

/* Sleep state performance counter disable */

#define MIPS_CONF6_SPCD		(_ULCAST_(1) << 14)

/* proAptiv FTLB on/off bit */

#define MIPS_CONF6_FTLBEN	(_ULCAST_(1) << 15)

/* Disable load/store bonding */

#define MIPS_CONF6_DLSB		(_ULCAST_(1) << 21)

/* Loongson-3 FTLB on/off bit */

#define MIPS_CONF6_FTLBDIS	(_ULCAST_(1) << 22)

/* FTLB probability bits */

arch/mips/kernel/spram.c

+2 −2
Original line number Diff line number Diff line
@@ -209,11 +209,11 @@ void spram_config(void) 
	case CPU_P6600:

		config0 = read_c0_config();

		/* FIXME: addresses are Malta specific */

		if (config0 & (1<<24)) {

		if (config0 & MIPS_CONF_ISP) {

			probe_spram("ISPRAM", 0x1c000000,

				    &ispram_load_tag, &ispram_store_tag);

		}

		if (config0 & (1<<23))

		if (config0 & MIPS_CONF_DSP)

			probe_spram("DSPRAM", 0x1c100000,

				    &dspram_load_tag, &dspram_store_tag);

	}

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