Commit 997af5df authored by Michal Kalderon's avatar Michal Kalderon Committed by David S. Miller
Browse files

qed: FW 8.42.2.0 Additional ll2 type 



LL2 queues were a limited resource due to FW constraints.
This FW introduced a new resource which is a context based ll2 queue
(memory on host). The additional ll2 queues are required for RDMA SRIOV.
The code refers to the previous ll2 queues as ram-based or legacy, and the
new queues as ctx-based.
This change decreased the "legacy" ram-based queues therefore the first ll2
queue used for iWARP was converted to the ctx-based ll2 queue.
This feature also exposed a bug in the DIRECT_REG_WR64 macro implementation
which didn't have an effect in other use cases.

Signed-off-by: default avatarAriel Elior <ariel.elior@marvell.com>
Signed-off-by: default avatarMichal Kalderon <michal.kalderon@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 804c5702

drivers/net/ethernet/qlogic/qed/qed.h

+2 −1
Original line number Diff line number Diff line
@@ -253,7 +253,8 @@ enum qed_resources { 
	QED_VLAN,

	QED_RDMA_CNQ_RAM,

	QED_ILT,

	QED_LL2_QUEUE,

	QED_LL2_RAM_QUEUE,

	QED_LL2_CTX_QUEUE,

	QED_CMDQS_CQS,

	QED_RDMA_STATS_QUEUE,

	QED_BDQ,

drivers/net/ethernet/qlogic/qed/qed_dev.c

+14 −6
Original line number Diff line number Diff line
@@ -3565,8 +3565,10 @@ const char *qed_hw_get_resc_name(enum qed_resources res_id) 
		return "RDMA_CNQ_RAM";

	case QED_ILT:

		return "ILT";

	case QED_LL2_QUEUE:

		return "LL2_QUEUE";

	case QED_LL2_RAM_QUEUE:

		return "LL2_RAM_QUEUE";

	case QED_LL2_CTX_QUEUE:

		return "LL2_CTX_QUEUE";

	case QED_CMDQS_CQS:

		return "CMDQS_CQS";

	case QED_RDMA_STATS_QUEUE:
@@ -3615,8 +3617,11 @@ qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 


	for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {

		switch (res_id) {

		case QED_LL2_QUEUE:

			resc_max_val = MAX_NUM_LL2_RX_QUEUES;

		case QED_LL2_RAM_QUEUE:

			resc_max_val = MAX_NUM_LL2_RX_RAM_QUEUES;

			break;

		case QED_LL2_CTX_QUEUE:

			resc_max_val = MAX_NUM_LL2_RX_CTX_QUEUES;

			break;

		case QED_RDMA_CNQ_RAM:

			/* No need for a case for QED_CMDQS_CQS since
@@ -3691,8 +3696,11 @@ int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn, 
		*p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :

			       PXP_NUM_ILT_RECORDS_BB) / num_funcs;

		break;

	case QED_LL2_QUEUE:

		*p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;

	case QED_LL2_RAM_QUEUE:

		*p_resc_num = MAX_NUM_LL2_RX_RAM_QUEUES / num_funcs;

		break;

	case QED_LL2_CTX_QUEUE:

		*p_resc_num = MAX_NUM_LL2_RX_CTX_QUEUES / num_funcs;

		break;

	case QED_RDMA_CNQ_RAM:

	case QED_CMDQS_CQS:

drivers/net/ethernet/qlogic/qed/qed_hsi.h

+37 −5
Original line number Diff line number Diff line
@@ -98,6 +98,7 @@ enum core_event_opcode { 
	CORE_EVENT_RX_QUEUE_STOP,

	CORE_EVENT_RX_QUEUE_FLUSH,

	CORE_EVENT_TX_QUEUE_UPDATE,

	CORE_EVENT_QUEUE_STATS_QUERY,

	MAX_CORE_EVENT_OPCODE

};
@@ -116,7 +117,7 @@ struct core_ll2_port_stats { 
	struct regpair gsi_crcchksm_error;

};



/* Ethernet TX Per Queue Stats */

/* LL2 TX Per Queue Stats */

struct core_ll2_pstorm_per_queue_stat {

	struct regpair sent_ucast_bytes;

	struct regpair sent_mcast_bytes;
@@ -124,13 +125,13 @@ struct core_ll2_pstorm_per_queue_stat { 
	struct regpair sent_ucast_pkts;

	struct regpair sent_mcast_pkts;

	struct regpair sent_bcast_pkts;

	struct regpair error_drop_pkts;

};



/* Light-L2 RX Producers in Tstorm RAM */

struct core_ll2_rx_prod {

	__le16 bd_prod;

	__le16 cqe_prod;

	__le32 reserved;

};



struct core_ll2_tstorm_per_queue_stat {
@@ -147,6 +148,18 @@ struct core_ll2_ustorm_per_queue_stat { 
	struct regpair rcv_bcast_pkts;

};



/* Structure for doorbell data, in PWM mode, for RX producers update. */

struct core_pwm_prod_update_data {

	__le16 icid; /* internal CID */

	u8 reserved0;

	u8 params;

#define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK	  0x3

#define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_SHIFT   0

#define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_MASK  0x3F	/* Set 0 */

#define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_SHIFT 2

	struct core_ll2_rx_prod prod; /* Producers */

};



/* Core Ramrod Command IDs (light L2) */

enum core_ramrod_cmd_id {

	CORE_RAMROD_UNUSED,
@@ -156,6 +169,7 @@ enum core_ramrod_cmd_id { 
	CORE_RAMROD_TX_QUEUE_STOP,

	CORE_RAMROD_RX_QUEUE_FLUSH,

	CORE_RAMROD_TX_QUEUE_UPDATE,

	CORE_RAMROD_QUEUE_STATS_QUERY,

	MAX_CORE_RAMROD_CMD_ID

};
@@ -274,8 +288,11 @@ struct core_rx_start_ramrod_data { 
	u8 mf_si_mcast_accept_all;

	struct core_rx_action_on_error action_on_error;

	u8 gsi_offload_flag;

	u8 vport_id_valid;

	u8 vport_id;

	u8 zero_prod_flg;

	u8 wipe_inner_vlan_pri_en;

	u8 reserved[5];

	u8 reserved[2];

};



/* Ramrod data for rx queue stop ramrod */
@@ -352,8 +369,11 @@ struct core_tx_start_ramrod_data { 
	__le16 pbl_size;

	__le16 qm_pq_id;

	u8 gsi_offload_flag;

	u8 ctx_stats_en;

	u8 vport_id_valid;

	u8 vport_id;

	u8 resrved[2];

	u8 enforce_security_flag;

	u8 reserved[7];

};



/* Ramrod data for tx queue stop ramrod */
@@ -761,7 +781,7 @@ struct e4_tstorm_core_conn_ag_ctx { 
	__le16 word1;

	__le16 word2;

	__le16 word3;

	__le32 reg9;

	__le32 ll2_rx_prod;

	__le32 reg10;

};
@@ -844,6 +864,11 @@ struct ustorm_core_conn_st_ctx { 
	__le32 reserved[4];

};



/* The core storm context for the Tstorm */

struct tstorm_core_conn_st_ctx {

	__le32 reserved[4];

};



/* core connection context */

struct e4_core_conn_context {

	struct ystorm_core_conn_st_ctx ystorm_st_context;
@@ -857,6 +882,8 @@ struct e4_core_conn_context { 
	struct mstorm_core_conn_st_ctx mstorm_st_context;

	struct ustorm_core_conn_st_ctx ustorm_st_context;

	struct regpair ustorm_st_padding[2];

	struct tstorm_core_conn_st_ctx tstorm_st_context;

	struct regpair tstorm_st_padding[2];

};



struct eth_mstorm_per_pf_stat {
@@ -12483,6 +12510,11 @@ enum resource_id_enum { 
	RESOURCE_LL2_QUEUE_E = 15,

	RESOURCE_RDMA_STATS_QUEUE_E = 16,

	RESOURCE_BDQ_E = 17,

	RESOURCE_QCN_E = 18,

	RESOURCE_LLH_FILTER_E = 19,

	RESOURCE_VF_MAC_ADDR = 20,

	RESOURCE_LL2_CQS_E = 21,

	RESOURCE_VF_CNQS = 22,

	RESOURCE_MAX_NUM,

	RESOURCE_NUM_INVALID = 0xFFFFFFFF

};

drivers/net/ethernet/qlogic/qed/qed_iscsi.c

+3 −2
Original line number Diff line number Diff line
@@ -213,7 +213,8 @@ qed_sp_iscsi_func_start(struct qed_hwfn *p_hwfn, 
	p_init->num_sq_pages_in_ring = p_params->num_sq_pages_in_ring;

	p_init->num_r2tq_pages_in_ring = p_params->num_r2tq_pages_in_ring;

	p_init->num_uhq_pages_in_ring = p_params->num_uhq_pages_in_ring;

	p_init->ll2_rx_queue_id = p_hwfn->hw_info.resc_start[QED_LL2_QUEUE] +

	p_init->ll2_rx_queue_id =

	    p_hwfn->hw_info.resc_start[QED_LL2_RAM_QUEUE] +

	    p_params->ll2_ooo_queue_id;



	p_init->func_params.log_page_size = p_params->log_page_size;

drivers/net/ethernet/qlogic/qed/qed_iwarp.c

+6 −2
Original line number Diff line number Diff line
@@ -137,7 +137,7 @@ qed_iwarp_init_fw_ramrod(struct qed_hwfn *p_hwfn, 
			 struct iwarp_init_func_ramrod_data *p_ramrod)

{

	p_ramrod->iwarp.ll2_ooo_q_index =

		RESC_START(p_hwfn, QED_LL2_QUEUE) +

	    RESC_START(p_hwfn, QED_LL2_RAM_QUEUE) +

	    p_hwfn->p_rdma_info->iwarp.ll2_ooo_handle;



	p_ramrod->tcp.max_fin_rt = QED_IWARP_MAX_FIN_RT_DEFAULT;
@@ -2651,6 +2651,8 @@ qed_iwarp_ll2_start(struct qed_hwfn *p_hwfn, 


	memset(&data, 0, sizeof(data));

	data.input.conn_type = QED_LL2_TYPE_IWARP;

	/* SYN will use ctx based queues */

	data.input.rx_conn_type = QED_LL2_RX_TYPE_CTX;

	data.input.mtu = params->max_mtu;

	data.input.rx_num_desc = QED_IWARP_LL2_SYN_RX_SIZE;

	data.input.tx_num_desc = QED_IWARP_LL2_SYN_TX_SIZE;
@@ -2683,6 +2685,8 @@ qed_iwarp_ll2_start(struct qed_hwfn *p_hwfn, 


	/* Start OOO connection */

	data.input.conn_type = QED_LL2_TYPE_OOO;

	/* OOO/unaligned will use legacy ll2 queues (ram based) */

	data.input.rx_conn_type = QED_LL2_RX_TYPE_LEGACY;

	data.input.mtu = params->max_mtu;



	n_ooo_bufs = (QED_IWARP_MAX_OOO * rcv_wnd_size) /

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