drm/amdgpu: update psp firmwares loading sequence V2 (995da6cc) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+59 −6

Original line number	Diff line number	Diff line
		@@ -38,6 +38,39 @@

		static void psp_set_funcs(struct amdgpu_device *adev);

		/*
		* Due to DF Cstate management centralized to PMFW, the firmware
		* loading sequence will be updated as below:
		* - Load KDB
		* - Load SYS_DRV
		* - Load tOS
		* - Load PMFW
		* - Setup TMR
		* - Load other non-psp fw
		* - Load ASD
		* - Load XGMI/RAS/HDCP/DTM TA if any
		*
		* This new sequence is required for
		* - Arcturus
		* - Navi12 and onwards
		*/
		static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
		{
		struct amdgpu_device *adev = psp->adev;

		psp->pmfw_centralized_cstate_management = false;

		if (amdgpu_sriov_vf(adev))
		return;

		if (adev->flags & AMD_IS_APU)
		return;

		if ((adev->asic_type == CHIP_ARCTURUS) \|\|
		(adev->asic_type >= CHIP_NAVI12))
		psp->pmfw_centralized_cstate_management = true;
		}

		static int psp_early_init(void *handle)
		{
		struct amdgpu_device adev = (struct amdgpu_device )handle;
		@@ -75,6 +108,8 @@ static int psp_early_init(void *handle)

		psp->adev = adev;

		psp_check_pmfw_centralized_cstate_management(psp);

		return 0;
		}

		@@ -1116,11 +1151,18 @@ static int psp_hw_start(struct psp_context *psp)
		return ret;
		}

		/*
		* For those ASICs with DF Cstate management centralized
		* to PMFW, TMR setup should be performed after PMFW
		* loaded and before other non-psp firmware loaded.
		*/
		if (!psp->pmfw_centralized_cstate_management) {
		ret = psp_tmr_load(psp);
		if (ret) {
		DRM_ERROR("PSP load tmr failed!\n");
		return ret;
		}
		}

		return 0;
		}
		@@ -1316,7 +1358,8 @@ static int psp_np_fw_load(struct psp_context *psp)
		struct amdgpu_firmware_info *ucode;
		struct amdgpu_device* adev = psp->adev;

		if (psp->autoload_supported) {
		if (psp->autoload_supported \|\|
		psp->pmfw_centralized_cstate_management) {
		ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
		if (!ucode->fw \|\| amdgpu_sriov_vf(adev))
		goto out;
		@@ -1326,6 +1369,14 @@ static int psp_np_fw_load(struct psp_context *psp)
		return ret;
		}

		if (psp->pmfw_centralized_cstate_management) {
		ret = psp_tmr_load(psp);
		if (ret) {
		DRM_ERROR("PSP load tmr failed!\n");
		return ret;
		}
		}

		out:
		for (i = 0; i < adev->firmware.max_ucodes; i++) {
		ucode = &adev->firmware.ucode[i];
		@@ -1333,7 +1384,9 @@ out:
		continue;

		if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
		(psp_smu_reload_quirk(psp) \|\| psp->autoload_supported))
		(psp_smu_reload_quirk(psp) \|\|
		psp->autoload_supported \|\|
		psp->pmfw_centralized_cstate_management))
		continue;

		if (amdgpu_sriov_vf(adev) &&

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -264,6 +264,8 @@ struct psp_context
		atomic_t fence_value;
		/* flag to mark whether gfx fw autoload is supported or not */
		bool autoload_supported;
		/* flag to mark whether df cstate management centralized to PMFW */
		bool pmfw_centralized_cstate_management;

		/* xgmi ta firmware and buffer */
		const struct firmware *ta_fw;

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