drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping (991d9557) · Commits · 戴 / test

For TGL, there is no need to keep DDI clock on till IO enabling for mipi dsi. Signed-off-by:

drivers/gpu/drm/i915/display/icl_dsi.c

+8 −2

Original line number	Diff line number	Diff line
		@@ -607,6 +607,9 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
		I915_WRITE(ICL_DPCLKA_CFGCR0, val);

		for_each_dsi_phy(phy, intel_dsi->phys) {
		if (INTEL_GEN(dev_priv) >= 12)
		val \|= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
		else
		val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
		}
		I915_WRITE(ICL_DPCLKA_CFGCR0, val);
		@@ -951,6 +954,8 @@ static void
		gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
		const struct intel_crtc_state *pipe_config)
		{
		struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

		/* step 4a: power up all lanes of the DDI used by DSI */
		gen11_dsi_power_up_lanes(encoder);

		@@ -973,6 +978,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
		gen11_dsi_configure_transcoder(encoder, pipe_config);

		/* Step 4l: Gate DDI clocks */
		if (IS_GEN(dev_priv, 11))
		gen11_dsi_gate_clocks(encoder);
		}