Commit 990a4007 authored by Archit Taneja's avatar Archit Taneja Committed by Rob Clark
Browse files

drm/msm/mdp5: Add MDSS top level driver 



SoCs that contain MDP5 have a top level wrapper called MDSS that manages
clocks, power and irq for the sub-blocks within it.

Currently, the MDSS portions are stuffed into the MDP5 driver. This makes
it hard to represent the DT bindings in the correct way. We create a top
level MDSS helper that handles these parts. This is essentially moving out
some of the mdp5_kms irq code and MDSS register space and keeping it as a
separate entity. We haven't given any clocks to the top level MDSS yet,
but a AHB clock would be added in the future to access registers.

One thing to note is that the resources allocated by this helper are
tied to the top level platform_device (the one that allocates the
drm_device struct too). This device would be the parent to MDSS
sub-blocks like MDP5, DSI, eDP etc.

Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent a2b3a557

drivers/gpu/drm/msm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ msm-y := \ 
	mdp/mdp5/mdp5_crtc.o \

	mdp/mdp5/mdp5_encoder.o \

	mdp/mdp5/mdp5_irq.o \

	mdp/mdp5/mdp5_mdss.o \

	mdp/mdp5/mdp5_kms.o \

	mdp/mdp5/mdp5_plane.o \

	mdp/mdp5/mdp5_smp.o \

drivers/gpu/drm/msm/mdp/mdp5/mdp5_mdss.c

0 → 100644
+223 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 as published by

 * the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#include <linux/irqdomain.h>

#include <linux/irq.h>



#include "msm_drv.h"

#include "mdp5_kms.h"



/*

 * If needed, this can become more specific: something like struct mdp5_mdss,

 * which contains a 'struct msm_mdss base' member.

 */

struct msm_mdss {

	struct drm_device *dev;



	void __iomem *mmio, *vbif;



	struct regulator *vdd;



	struct {

		volatile unsigned long enabled_mask;

		struct irq_domain *domain;

	} irqcontroller;

};



static inline void mdss_write(struct msm_mdss *mdss, u32 reg, u32 data)

{

	msm_writel(data, mdss->mmio + reg);

}



static inline u32 mdss_read(struct msm_mdss *mdss, u32 reg)

{

	return msm_readl(mdss->mmio + reg);

}



static irqreturn_t mdss_irq(int irq, void *arg)

{

	struct msm_mdss *mdss = arg;

	u32 intr;



	intr = mdss_read(mdss, REG_MDSS_HW_INTR_STATUS);



	VERB("intr=%08x", intr);



	while (intr) {

		irq_hw_number_t hwirq = fls(intr) - 1;



		generic_handle_irq(irq_find_mapping(

				mdss->irqcontroller.domain, hwirq));

		intr &= ~(1 << hwirq);

	}



	return IRQ_HANDLED;

}



/*

 * interrupt-controller implementation, so sub-blocks (MDP/HDMI/eDP/DSI/etc)

 * can register to get their irq's delivered

 */



#define VALID_IRQS  (MDSS_HW_INTR_STATUS_INTR_MDP | \

		MDSS_HW_INTR_STATUS_INTR_DSI0 | \

		MDSS_HW_INTR_STATUS_INTR_DSI1 | \

		MDSS_HW_INTR_STATUS_INTR_HDMI | \

		MDSS_HW_INTR_STATUS_INTR_EDP)



static void mdss_hw_mask_irq(struct irq_data *irqd)

{

	struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd);



	smp_mb__before_atomic();

	clear_bit(irqd->hwirq, &mdss->irqcontroller.enabled_mask);

	smp_mb__after_atomic();

}



static void mdss_hw_unmask_irq(struct irq_data *irqd)

{

	struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd);



	smp_mb__before_atomic();

	set_bit(irqd->hwirq, &mdss->irqcontroller.enabled_mask);

	smp_mb__after_atomic();

}



static struct irq_chip mdss_hw_irq_chip = {

	.name		= "mdss",

	.irq_mask	= mdss_hw_mask_irq,

	.irq_unmask	= mdss_hw_unmask_irq,

};



static int mdss_hw_irqdomain_map(struct irq_domain *d, unsigned int irq,

				 irq_hw_number_t hwirq)

{

	struct msm_mdss *mdss = d->host_data;



	if (!(VALID_IRQS & (1 << hwirq)))

		return -EPERM;



	irq_set_chip_and_handler(irq, &mdss_hw_irq_chip, handle_level_irq);

	irq_set_chip_data(irq, mdss);



	return 0;

}



static struct irq_domain_ops mdss_hw_irqdomain_ops = {

	.map = mdss_hw_irqdomain_map,

	.xlate = irq_domain_xlate_onecell,

};





static int mdss_irq_domain_init(struct msm_mdss *mdss)

{

	struct device *dev = mdss->dev->dev;

	struct irq_domain *d;



	d = irq_domain_add_linear(dev->of_node, 32, &mdss_hw_irqdomain_ops,

				  mdss);

	if (!d) {

		dev_err(dev, "mdss irq domain add failed\n");

		return -ENXIO;

	}



	mdss->irqcontroller.enabled_mask = 0;

	mdss->irqcontroller.domain = d;



	return 0;

}



void msm_mdss_destroy(struct drm_device *dev)

{

	struct msm_drm_private *priv = dev->dev_private;

	struct msm_mdss *mdss = priv->mdss;



	if (!mdss)

		return;



	irq_domain_remove(mdss->irqcontroller.domain);

	mdss->irqcontroller.domain = NULL;



	regulator_disable(mdss->vdd);

}



int msm_mdss_init(struct drm_device *dev)

{

	struct platform_device *pdev = dev->platformdev;

	struct msm_drm_private *priv = dev->dev_private;

	struct msm_mdss *mdss;

	int ret;



	DBG("");



	if (!of_device_is_compatible(dev->dev->of_node, "qcom,mdss"))

		return 0;



	mdss = devm_kzalloc(dev->dev, sizeof(*mdss), GFP_KERNEL);

	if (!mdss) {

		ret = -ENOMEM;

		goto fail;

	}



	mdss->dev = dev;



	mdss->mmio = msm_ioremap(pdev, "mdss_phys", "MDSS");

	if (IS_ERR(mdss->mmio)) {

		ret = PTR_ERR(mdss->mmio);

		goto fail;

	}



	mdss->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF");

	if (IS_ERR(mdss->vbif)) {

		ret = PTR_ERR(mdss->vbif);

		goto fail;

	}



	/* Regulator to enable GDSCs in downstream kernels */

	mdss->vdd = devm_regulator_get(dev->dev, "vdd");

	if (IS_ERR(mdss->vdd)) {

		ret = PTR_ERR(mdss->vdd);

		goto fail;

	}



	ret = regulator_enable(mdss->vdd);

	if (ret) {

		dev_err(dev->dev, "failed to enable regulator vdd: %d\n",

			ret);

		goto fail;

	}



	ret = devm_request_irq(dev->dev, platform_get_irq(pdev, 0),

			       mdss_irq, 0, "mdss_isr", mdss);

	if (ret) {

		dev_err(dev->dev, "failed to init irq: %d\n", ret);

		goto fail_irq;

	}



	ret = mdss_irq_domain_init(mdss);

	if (ret) {

		dev_err(dev->dev, "failed to init sub-block irqs: %d\n", ret);

		goto fail_irq;

	}



	priv->mdss = mdss;



	return 0;

fail_irq:

	regulator_disable(mdss->vdd);

fail:

	return ret;

}

drivers/gpu/drm/msm/msm_drv.h

+4 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ 
struct msm_kms;

struct msm_gpu;

struct msm_mmu;

struct msm_mdss;

struct msm_rd_state;

struct msm_perf_state;

struct msm_gem_submit;
@@ -82,6 +83,9 @@ struct msm_drm_private { 
	/* subordinate devices, if present: */

	struct platform_device *gpu_pdev;



	/* top level MDSS wrapper device (for MDP5 only) */

	struct msm_mdss *mdss;



	/* possibly this should be in the kms component, but it is

	 * shared by both mdp4 and mdp5..

	 */

drivers/gpu/drm/msm/msm_kms.h

+2 −0
Original line number Diff line number Diff line
@@ -73,5 +73,7 @@ static inline void msm_kms_init(struct msm_kms *kms, 


struct msm_kms *mdp4_kms_init(struct drm_device *dev);

struct msm_kms *mdp5_kms_init(struct drm_device *dev);

int msm_mdss_init(struct drm_device *dev);

void msm_mdss_destroy(struct drm_device *dev);



#endif /* __MSM_KMS_H__ */

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