Commit 9908c826 authored by Madhavan Srinivasan's avatar Madhavan Srinivasan Committed by Michael Ellerman
Browse files

powerpc/perf: Add Power10 PMU feature to DT CPU features 



Add Power10 feature function to DT CPU features, along with a Power10
specific init() to initialize PMU SPRs, sets the oprofile_cpu_type and
cpu_features. This will enable performance monitoring unit (PMU) for
Power10 in CPU features with "performance-monitor-power10".

For Power ISA v3.1, BHRB disable is controlled via Monitor Mode
Control Register A (MMCRA) bit, namely "BHRB Recording
Disable (BHRBRD)". This patch initializes MMCRA BHRBRD to disable BHRB
feature at boot for Power10.

Signed-off-by: default avatarMadhavan Srinivasan <maddy@linux.ibm.com>
[mpe: Move MMCRA_BHRB_DISABLE as noted by jpn, drop CPU setup changes]
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1594996707-3727-8-git-send-email-atrajeev@linux.vnet.ibm.com
parent 1979ae8c

arch/powerpc/include/asm/reg.h

+1 −0
Original line number Diff line number Diff line
@@ -888,6 +888,7 @@ 
#define   MMCRA_SLOT	0x07000000UL /* SLOT bits (37-39) */

#define   MMCRA_SLOT_SHIFT	24

#define   MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */

#define   MMCRA_BHRB_DISABLE  0x2000000000UL // BHRB disable bit for ISA v3.1

#define   POWER6_MMCRA_SDSYNC 0x0000080000000000ULL	/* SDAR/SIAR synced */

#define   POWER6_MMCRA_SIHV   0x0000040000000000ULL

#define   POWER6_MMCRA_SIPR   0x0000020000000000ULL

arch/powerpc/kernel/dt_cpu_ftrs.c

+26 −0
Original line number Diff line number Diff line
@@ -450,6 +450,31 @@ static int __init feat_enable_pmu_power9(struct dt_cpu_feature *f) 
	return 1;

}



static void init_pmu_power10(void)

{

	init_pmu_power9();



	mtspr(SPRN_MMCR3, 0);

	mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE);

}



static int __init feat_enable_pmu_power10(struct dt_cpu_feature *f)

{

	hfscr_pmu_enable();



	init_pmu_power10();

	init_pmu_registers = init_pmu_power10;



	cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA;

	cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT;



	cur_cpu_spec->num_pmcs          = 6;

	cur_cpu_spec->pmc_type          = PPC_PMC_IBM;

	cur_cpu_spec->oprofile_cpu_type = "ppc64/power10";



	return 1;

}



static int __init feat_enable_tm(struct dt_cpu_feature *f)

{

#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
@@ -639,6 +664,7 @@ static struct dt_cpu_feature_match __initdata 
	{"pc-relative-addressing", feat_enable, 0},

	{"machine-check-power9", feat_enable_mce_power9, 0},

	{"performance-monitor-power9", feat_enable_pmu_power9, 0},

	{"performance-monitor-power10", feat_enable_pmu_power10, 0},

	{"event-based-branch-v3", feat_enable, 0},

	{"random-number-generator", feat_enable, 0},

	{"system-call-vectored", feat_disable, 0},

arch/powerpc/perf/core-book3s.c

+1 −0
Original line number Diff line number Diff line
@@ -94,6 +94,7 @@ static unsigned int freeze_events_kernel = MMCR0_FCS; 
#define SPRN_SIER2		0

#define SPRN_SIER3		0

#define MMCRA_SAMPLE_ENABLE	0

#define MMCRA_BHRB_DISABLE     0



static inline unsigned long perf_ip_adjust(struct pt_regs *regs)

{

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