drm/i915/dpll_mgr: switch to kernel types

{

	const enum intel_dpll_id id = pll->info->id;

	intel_wakeref_t wakeref;

	uint32_t val;

	u32 val;

	wakeref = intel_display_power_get_if_enabled(dev_priv,

						     POWER_DOMAIN_PLLS);

				  struct intel_shared_dpll *pll)

{

	const enum intel_dpll_id id = pll->info->id;

	uint32_t val;

	u32 val;

	val = I915_READ(WRPLL_CTL(id));

	I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE);

static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,

				 struct intel_shared_dpll *pll)

{

	uint32_t val;

	u32 val;

	val = I915_READ(SPLL_CTL);

	I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);

{

	const enum intel_dpll_id id = pll->info->id;

	intel_wakeref_t wakeref;

	uint32_t val;

	u32 val;

	wakeref = intel_display_power_get_if_enabled(dev_priv,

						     POWER_DOMAIN_PLLS);

				      struct intel_dpll_hw_state *hw_state)

{

	intel_wakeref_t wakeref;

	uint32_t val;

	u32 val;

	wakeref = intel_display_power_get_if_enabled(dev_priv,

						     POWER_DOMAIN_PLLS);

	return budget;

}

static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,

				 unsigned r2, unsigned n2, unsigned p,

static void hsw_wrpll_update_rnp(u64 freq2k, unsigned int budget,

				 unsigned int r2, unsigned int n2,

				 unsigned int p,

				 struct hsw_wrpll_rnp *best)

{

	uint64_t a, b, c, d, diff, diff_best;

	u64 a, b, c, d, diff, diff_best;

	/* No best (r,n,p) yet */

	if (best->p == 0) {

hsw_ddi_calculate_wrpll(int clock /* in Hz */,

			unsigned *r2_out, unsigned *n2_out, unsigned *p_out)

{

	uint64_t freq2k;

	u64 freq2k;

	unsigned p, n2, r2;

	struct hsw_wrpll_rnp best = { 0, 0, 0 };

	unsigned budget;

						       struct intel_crtc_state *crtc_state)

{

	struct intel_shared_dpll *pll;

	uint32_t val;

	u32 val;

	unsigned int p, n2, r2;

	hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);

				    struct intel_shared_dpll *pll)

{

	const enum intel_dpll_id id = pll->info->id;

	uint32_t val;

	u32 val;

	val = I915_READ(DPLL_CTRL1);

				     struct intel_shared_dpll *pll,

				     struct intel_dpll_hw_state *hw_state)

{

	uint32_t val;

	u32 val;

	const struct skl_dpll_regs *regs = skl_dpll_regs;

	const enum intel_dpll_id id = pll->info->id;

	intel_wakeref_t wakeref;

	const struct skl_dpll_regs *regs = skl_dpll_regs;

	const enum intel_dpll_id id = pll->info->id;

	intel_wakeref_t wakeref;

	uint32_t val;

	u32 val;

	bool ret;

	wakeref = intel_display_power_get_if_enabled(dev_priv,

}

struct skl_wrpll_context {

	uint64_t min_deviation;		/* current minimal deviation */

	uint64_t central_freq;		/* chosen central freq */

	uint64_t dco_freq;		/* chosen dco freq */

	u64 min_deviation;		/* current minimal deviation */

	u64 central_freq;		/* chosen central freq */

	u64 dco_freq;			/* chosen dco freq */

	unsigned int p;			/* chosen divider */

};

#define SKL_DCO_MAX_NDEVIATION	600

static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,

				  uint64_t central_freq,

				  uint64_t dco_freq,

				  u64 central_freq,

				  u64 dco_freq,

				  unsigned int divider)

{

	uint64_t deviation;

	u64 deviation;

	deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),

			      central_freq);

}

struct skl_wrpll_params {

	uint32_t        dco_fraction;

	uint32_t        dco_integer;

	uint32_t        qdiv_ratio;

	uint32_t        qdiv_mode;

	uint32_t        kdiv;

	uint32_t        pdiv;

	uint32_t        central_freq;

	u32 dco_fraction;

	u32 dco_integer;

	u32 qdiv_ratio;

	u32 qdiv_mode;

	u32 kdiv;

	u32 pdiv;

	u32 central_freq;

};

static void skl_wrpll_params_populate(struct skl_wrpll_params *params,

				      uint64_t afe_clock,

				      uint64_t central_freq,

				      uint32_t p0, uint32_t p1, uint32_t p2)

				      u64 afe_clock,

				      u64 central_freq,

				      u32 p0, u32 p1, u32 p2)

{

	uint64_t dco_freq;

	u64 dco_freq;

	switch (central_freq) {

	case 9600000000ULL:

skl_ddi_calculate_wrpll(int clock /* in Hz */,

			struct skl_wrpll_params *wrpll_params)

{

	uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */

	uint64_t dco_central_freq[3] = {8400000000ULL,

	u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */

	u64 dco_central_freq[3] = { 8400000000ULL,

				    9000000000ULL,

				    9600000000ULL };

	static const int even_dividers[] = {  4,  6,  8, 10, 12, 14, 16, 18, 20,

		for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {

			for (i = 0; i < dividers[d].n_dividers; i++) {

				unsigned int p = dividers[d].list[i];

				uint64_t dco_freq = p * afe_clock;

				u64 dco_freq = p * afe_clock;

				skl_wrpll_try_divider(&ctx,

						      dco_central_freq[dco],

				      struct intel_crtc_state *crtc_state,

				      int clock)

{

	uint32_t ctrl1, cfgcr1, cfgcr2;

	u32 ctrl1, cfgcr1, cfgcr2;

	struct skl_wrpll_params wrpll_params = { 0, };

	/*

skl_ddi_dp_set_dpll_hw_state(int clock,

			     struct intel_dpll_hw_state *dpll_hw_state)

{

	uint32_t ctrl1;

	u32 ctrl1;

	/*

	 * See comment in intel_dpll_hw_state to understand why we always use 0

static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,

				struct intel_shared_dpll *pll)

{

	uint32_t temp;

	u32 temp;

	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */

	enum dpio_phy phy;

	enum dpio_channel ch;

					struct intel_shared_dpll *pll)

{

	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */

	uint32_t temp;

	u32 temp;

	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));

	temp &= ~PORT_PLL_ENABLE;

	intel_wakeref_t wakeref;

	enum dpio_phy phy;

	enum dpio_channel ch;

	uint32_t val;

	u32 val;

	bool ret;

	bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);

/* bxt clock parameters */

struct bxt_clk_div {

	int clock;

	uint32_t p1;

	uint32_t p2;

	uint32_t m2_int;

	uint32_t m2_frac;

	u32 p1;

	u32 p2;

	u32 m2_int;

	u32 m2_frac;

	bool m2_frac_en;

	uint32_t n;

	u32 n;

	int vco;

};

			  struct intel_dpll_hw_state *dpll_hw_state)

{

	int vco = clk_div->vco;

	uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;

	uint32_t lanestagger;

	u32 prop_coef, int_coef, gain_ctl, targ_cnt;

	u32 lanestagger;

	if (vco >= 6200000 && vco <= 6700000) {

		prop_coef = 4;

	struct drm_i915_private *dev_priv = to_i915(dev);

	if (INTEL_GEN(dev_priv) < 9) {

		uint32_t val = I915_READ(LCPLL_CTL);

		u32 val = I915_READ(LCPLL_CTL);

		/*

		 * The LCPLL register should be turned on by the BIOS. For now

			       struct intel_shared_dpll *pll)

{

	const enum intel_dpll_id id = pll->info->id;

	uint32_t val;

	u32 val;

	/* 1. Enable DPLL power in DPLL_ENABLE. */

	val = I915_READ(CNL_DPLL_ENABLE(id));

				struct intel_shared_dpll *pll)

{

	const enum intel_dpll_id id = pll->info->id;

	uint32_t val;

	u32 val;

	/*

	 * 1. Configure DPCLKA_CFGCR0 to turn off the clock for the DDI.

{

	const enum intel_dpll_id id = pll->info->id;

	intel_wakeref_t wakeref;

	uint32_t val;

	u32 val;

	bool ret;

	wakeref = intel_display_power_get_if_enabled(dev_priv,

			struct skl_wrpll_params *wrpll_params)

{

	u32 afe_clock = clock * 5;

	uint32_t ref_clock;

	u32 ref_clock;

	u32 dco_min = 7998000;

	u32 dco_max = 10000000;

	u32 dco_mid = (dco_min + dco_max) / 2;

				      int clock)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	uint32_t cfgcr0, cfgcr1;

	u32 cfgcr0, cfgcr1;

	struct skl_wrpll_params wrpll_params = { 0, };

	cfgcr0 = DPLL_CFGCR0_HDMI_MODE;

cnl_ddi_dp_set_dpll_hw_state(int clock,

			     struct intel_dpll_hw_state *dpll_hw_state)

{

	uint32_t cfgcr0;

	u32 cfgcr0;

	cfgcr0 = DPLL_CFGCR0_SSC_ENABLE;

				struct intel_dpll_hw_state *pll_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	uint32_t cfgcr0, cfgcr1;

	u32 cfgcr0, cfgcr1;

	struct skl_wrpll_params pll_params = { 0 };

	bool ret;

}

int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,

			       uint32_t pll_id)

			       u32 pll_id)

{

	uint32_t cfgcr0, cfgcr1;

	uint32_t pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer, dco_fraction;

	u32 cfgcr0, cfgcr1;

	u32 pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer, dco_fraction;

	const struct skl_wrpll_params *params;

	int index, n_entries, link_clock;

}

static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,

				     uint32_t *target_dco_khz,

				     u32 *target_dco_khz,

				     struct intel_dpll_hw_state *state)

{

	uint32_t dco_min_freq, dco_max_freq;

	u32 dco_min_freq, dco_max_freq;

	int div1_vals[] = {7, 5, 3, 2};

	unsigned int i;

	int div2;

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	int refclk_khz = dev_priv->cdclk.hw.ref;

	uint32_t dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;

	uint32_t iref_ndiv, iref_trim, iref_pulse_w;

	uint32_t prop_coeff, int_coeff;

	uint32_t tdc_targetcnt, feedfwgain;

	uint64_t ssc_stepsize, ssc_steplen, ssc_steplog;

	uint64_t tmp;

	u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;

	u32 iref_ndiv, iref_trim, iref_pulse_w;

	u32 prop_coeff, int_coeff;

	u32 tdc_targetcnt, feedfwgain;

	u64 ssc_stepsize, ssc_steplen, ssc_steplog;

	u64 tmp;

	bool use_ssc = false;

	bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);

	}

	m2div_rem = dco_khz % (refclk_khz * m1div);

	tmp = (uint64_t)m2div_rem * (1 << 22);

	tmp = (u64)m2div_rem * (1 << 22);

	do_div(tmp, refclk_khz * m1div);

	m2div_frac = tmp;

	}

	if (use_ssc) {

		tmp = (uint64_t)dco_khz * 47 * 32;

		tmp = (u64)dco_khz * 47 * 32;

		do_div(tmp, refclk_khz * m1div * 10000);

		ssc_stepsize = tmp;

		tmp = (uint64_t)dco_khz * 1000;

		tmp = (u64)dco_khz * 1000;

		ssc_steplen = DIV_ROUND_UP_ULL(tmp, 32 * 2 * 32);

	} else {

		ssc_stepsize = 0;

	intel_wakeref_t wakeref;

	bool ret = false;

	enum port port;

	uint32_t val;

	u32 val;

	wakeref = intel_display_power_get_if_enabled(dev_priv,

						     POWER_DOMAIN_PLLS);

{

	const enum intel_dpll_id id = pll->info->id;

	i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id);

	uint32_t val;

	u32 val;

	val = I915_READ(enable_reg);

	val |= PLL_POWER_ENABLE;

{

	const enum intel_dpll_id id = pll->info->id;

	i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id);

	uint32_t val;

	u32 val;

	/* The first steps are done by intel_ddi_post_disable(). */

struct intel_dpll_hw_state {

	/* i9xx, pch plls */

	uint32_t dpll;

	uint32_t dpll_md;

	uint32_t fp0;

	uint32_t fp1;

	u32 dpll;

	u32 dpll_md;

	u32 fp0;

	u32 fp1;

	/* hsw, bdw */

	uint32_t wrpll;

	uint32_t spll;

	u32 wrpll;

	u32 spll;

	/* skl */

	/*

	 * the register.  This allows us to easily compare the state to share

	 * the DPLL.

	 */

	uint32_t ctrl1;

	u32 ctrl1;

	/* HDMI only, 0 when used for DP */

	uint32_t cfgcr1, cfgcr2;

	u32 cfgcr1, cfgcr2;

	/* cnl */

	uint32_t cfgcr0;

	u32 cfgcr0;

	/* CNL also uses cfgcr1 */

	/* bxt */

	uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,

		 pcsdw12;

	u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;

	/*

	 * ICL uses the following, already defined:

	 * uint32_t cfgcr0, cfgcr1;

	 */

	uint32_t mg_refclkin_ctl;

	uint32_t mg_clktop2_coreclkctl1;

	uint32_t mg_clktop2_hsclkctl;

	uint32_t mg_pll_div0;

	uint32_t mg_pll_div1;

	uint32_t mg_pll_lf;

	uint32_t mg_pll_frac_lock;

	uint32_t mg_pll_ssc;

	uint32_t mg_pll_bias;

	uint32_t mg_pll_tdc_coldst_bias;

	uint32_t mg_pll_bias_mask;

	uint32_t mg_pll_tdc_coldst_bias_mask;

	 * u32 cfgcr0, cfgcr1;

	 */

	u32 mg_refclkin_ctl;

	u32 mg_clktop2_coreclkctl1;

	u32 mg_clktop2_hsclkctl;

	u32 mg_pll_div0;

	u32 mg_pll_div1;

	u32 mg_pll_lf;

	u32 mg_pll_frac_lock;

	u32 mg_pll_ssc;

	u32 mg_pll_bias;

	u32 mg_pll_tdc_coldst_bias;

	u32 mg_pll_bias_mask;

	u32 mg_pll_tdc_coldst_bias_mask;

};

/**

	 *     Inform the state checker that the DPLL is kept enabled even if

	 *     not in use by any CRTC.

	 */

	uint32_t flags;

	u32 flags;

};

/**

void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,

			      struct intel_dpll_hw_state *hw_state);

int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,

			       uint32_t pll_id);

			       u32 pll_id);

int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);

enum intel_dpll_id icl_port_to_mg_pll_id(enum port port);

bool intel_dpll_is_combophy(enum intel_dpll_id id);