Commit 98c9cdfd authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2018-11-22' of... 

Merge tag 'drm-intel-fixes-2018-11-22' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

- Fix for fastboot DSI panel boot time flicker regression, also fixes Bugzilla #108225
- Fix Bugzilla #101269 to avoid GPU hangs on Sandybridge machines
- Avoid GPU hang on error capture on Broxton with Vt-d enabled
- Avoid missing GPU relocations on Pineview and Bearlake (Gen3)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181122120555.GA18282@jlahtine-desk.ger.corp.intel.com
parents 8cf6f361 f559156c

drivers/gpu/drm/i915/i915_gem_execbuffer.c

+6 −1
Original line number Original line Diff line number Diff line
@@ -1268,7 +1268,7 @@ relocate_entry(struct i915_vma *vma, 
		else if (gen >= 4)

		else if (gen >= 4)

			len = 4;

			len = 4;

		else

		else

			len = 3;

			len = 6;





		batch = reloc_gpu(eb, vma, len);

		batch = reloc_gpu(eb, vma, len);

		if (IS_ERR(batch))

		if (IS_ERR(batch))
@@ -1309,6 +1309,11 @@ relocate_entry(struct i915_vma *vma, 
			*batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;

			*batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;

			*batch++ = addr;

			*batch++ = addr;

			*batch++ = target_offset;

			*batch++ = target_offset;



			/* And again for good measure (blb/pnv) */

			*batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;

			*batch++ = addr;

			*batch++ = target_offset;

		}

		}





		goto out;

		goto out;

drivers/gpu/drm/i915/i915_gem_gtt.c

+5 −0
Original line number Original line Diff line number Diff line
@@ -3413,6 +3413,11 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) 
		ggtt->vm.insert_page    = bxt_vtd_ggtt_insert_page__BKL;

		ggtt->vm.insert_page    = bxt_vtd_ggtt_insert_page__BKL;

		if (ggtt->vm.clear_range != nop_clear_range)

		if (ggtt->vm.clear_range != nop_clear_range)

			ggtt->vm.clear_range = bxt_vtd_ggtt_clear_range__BKL;

			ggtt->vm.clear_range = bxt_vtd_ggtt_clear_range__BKL;



		/* Prevent recursively calling stop_machine() and deadlocks. */

		dev_info(dev_priv->drm.dev,

			 "Disabling error capture for VT-d workaround\n");

		i915_disable_error_state(dev_priv, -ENODEV);

	}

	}





	ggtt->invalidate = gen6_ggtt_invalidate;

	ggtt->invalidate = gen6_ggtt_invalidate;

drivers/gpu/drm/i915/i915_gpu_error.c

+14 −1
Original line number Original line Diff line number Diff line
@@ -648,6 +648,9 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, 
		return 0;

		return 0;

	}

	}





	if (IS_ERR(error))

		return PTR_ERR(error);



	if (*error->error_msg)

	if (*error->error_msg)

		err_printf(m, "%s\n", error->error_msg);

		err_printf(m, "%s\n", error->error_msg);

	err_printf(m, "Kernel: " UTS_RELEASE "\n");

	err_printf(m, "Kernel: " UTS_RELEASE "\n");
@@ -1859,6 +1862,7 @@ void i915_capture_error_state(struct drm_i915_private *i915, 
	error = i915_capture_gpu_state(i915);

	error = i915_capture_gpu_state(i915);

	if (!error) {

	if (!error) {

		DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");

		DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");

		i915_disable_error_state(i915, -ENOMEM);

		return;

		return;

	}

	}
@@ -1914,5 +1918,14 @@ void i915_reset_error_state(struct drm_i915_private *i915) 
	i915->gpu_error.first_error = NULL;

	i915->gpu_error.first_error = NULL;

	spin_unlock_irq(&i915->gpu_error.lock);

	spin_unlock_irq(&i915->gpu_error.lock);





	if (!IS_ERR(error))

		i915_gpu_state_put(error);

		i915_gpu_state_put(error);

}

}



void i915_disable_error_state(struct drm_i915_private *i915, int err)

{

	spin_lock_irq(&i915->gpu_error.lock);

	if (!i915->gpu_error.first_error)

		i915->gpu_error.first_error = ERR_PTR(err);

	spin_unlock_irq(&i915->gpu_error.lock);

}

drivers/gpu/drm/i915/i915_gpu_error.h

+7 −1
Original line number Original line Diff line number Diff line
@@ -343,6 +343,7 @@ static inline void i915_gpu_state_put(struct i915_gpu_state *gpu) 




struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);

struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);

void i915_reset_error_state(struct drm_i915_private *i915);

void i915_reset_error_state(struct drm_i915_private *i915);

void i915_disable_error_state(struct drm_i915_private *i915, int err);





#else

#else
@@ -355,13 +356,18 @@ static inline void i915_capture_error_state(struct drm_i915_private *dev_priv, 
static inline struct i915_gpu_state *

static inline struct i915_gpu_state *

i915_first_error_state(struct drm_i915_private *i915)

i915_first_error_state(struct drm_i915_private *i915)

{

{

	return NULL;

	return ERR_PTR(-ENODEV);

}

}





static inline void i915_reset_error_state(struct drm_i915_private *i915)

static inline void i915_reset_error_state(struct drm_i915_private *i915)

{

{

}

}





static inline void i915_disable_error_state(struct drm_i915_private *i915,

					    int err)

{

}



#endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */

#endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */





#endif /* _I915_GPU_ERROR_H_ */
 
#endif /* _I915_GPU_ERROR_H_ */

drivers/gpu/drm/i915/intel_display.c

+39 −0
Original line number Original line Diff line number Diff line
@@ -2890,6 +2890,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, 
	return;

	return;





valid_fb:

valid_fb:

	intel_state->base.rotation = plane_config->rotation;

	intel_fill_fb_ggtt_view(&intel_state->view, fb,

	intel_fill_fb_ggtt_view(&intel_state->view, fb,

				intel_state->base.rotation);

				intel_state->base.rotation);

	intel_state->color_plane[0].stride =

	intel_state->color_plane[0].stride =
@@ -7882,8 +7883,15 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, 
			plane_config->tiling = I915_TILING_X;

			plane_config->tiling = I915_TILING_X;

			fb->modifier = I915_FORMAT_MOD_X_TILED;

			fb->modifier = I915_FORMAT_MOD_X_TILED;

		}

		}



		if (val & DISPPLANE_ROTATE_180)

			plane_config->rotation = DRM_MODE_ROTATE_180;

	}

	}





	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&

	    val & DISPPLANE_MIRROR)

		plane_config->rotation |= DRM_MODE_REFLECT_X;



	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;

	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;

	fourcc = i9xx_format_to_fourcc(pixel_format);

	fourcc = i9xx_format_to_fourcc(pixel_format);

	fb->format = drm_format_info(fourcc);

	fb->format = drm_format_info(fourcc);
@@ -8952,6 +8960,29 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, 
		goto error;

		goto error;

	}

	}





	/*

	 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr

	 * while i915 HW rotation is clockwise, thats why this swapping.

	 */

	switch (val & PLANE_CTL_ROTATE_MASK) {

	case PLANE_CTL_ROTATE_0:

		plane_config->rotation = DRM_MODE_ROTATE_0;

		break;

	case PLANE_CTL_ROTATE_90:

		plane_config->rotation = DRM_MODE_ROTATE_270;

		break;

	case PLANE_CTL_ROTATE_180:

		plane_config->rotation = DRM_MODE_ROTATE_180;

		break;

	case PLANE_CTL_ROTATE_270:

		plane_config->rotation = DRM_MODE_ROTATE_90;

		break;

	}



	if (INTEL_GEN(dev_priv) >= 10 &&

	    val & PLANE_CTL_FLIP_HORIZONTAL)

		plane_config->rotation |= DRM_MODE_REFLECT_X;



	base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;

	base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;

	plane_config->base = base;

	plane_config->base = base;
@@ -15267,6 +15298,14 @@ retry: 
			ret = drm_atomic_add_affected_planes(state, crtc);

			ret = drm_atomic_add_affected_planes(state, crtc);

			if (ret)

			if (ret)

				goto out;

				goto out;



			/*

			 * FIXME hack to force a LUT update to avoid the

			 * plane update forcing the pipe gamma on without

			 * having a proper LUT loaded. Remove once we

			 * have readout for pipe gamma enable.

			 */

			crtc_state->color_mgmt_changed = true;

		}

		}

	}

	}

CRA Git | Maintained and supported by SUSTech CRA and CCSE