Commit 98c45f51 authored by Paul Mackerras's avatar Paul Mackerras Committed by Michael Ellerman
Browse files

selftests/powerpc/64: Test all paths through copy routines 



The hand-coded assembler 64-bit copy routines include feature sections
that select one code path or another depending on which CPU we are
executing on.  The self-tests for these copy routines end up testing
just one path.  This adds a mechanism for selecting any desired code
path at compile time, and makes 2 or 3 versions of each test, each
using a different code path, so as to cover all the possible paths.

Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
[mpe: Add -mcpu=power4 to CFLAGS for older compilers]
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent a7c81ce3

arch/powerpc/lib/copyuser_64.S

+7 −0
Original line number Diff line number Diff line
@@ -12,6 +12,11 @@ 
#include <asm/asm-compat.h>

#include <asm/feature-fixups.h>



#ifndef SELFTEST_CASE

/* 0 == most CPUs, 1 == POWER6, 2 == Cell */

#define SELFTEST_CASE	0

#endif



#ifdef __BIG_ENDIAN__

#define sLd sld		/* Shift towards low-numbered address. */

#define sHd srd		/* Shift towards high-numbered address. */
@@ -73,6 +78,7 @@ _GLOBAL(__copy_tofrom_user_base) 
 * At the time of writing the only CPU that has this combination of bits

 * set is Power6.

 */

test_feature = (SELFTEST_CASE == 1)

BEGIN_FTR_SECTION

	nop

FTR_SECTION_ELSE
@@ -82,6 +88,7 @@ ALT_FTR_SECTION_END(CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_CP_USE_DCBTZ, \ 
.Ldst_aligned:

	addi	r3,r3,-16

r3_offset = 16

test_feature = (SELFTEST_CASE == 0)

BEGIN_FTR_SECTION

	andi.	r0,r4,7

	bne	.Lsrc_unaligned

arch/powerpc/lib/copyuser_power7.S

+11 −10
Original line number Diff line number Diff line
@@ -19,6 +19,11 @@ 
 */

#include <asm/ppc_asm.h>



#ifndef SELFTEST_CASE

/* 0 == don't use VMX, 1 == use VMX */

#define SELFTEST_CASE	0

#endif



#ifdef __BIG_ENDIAN__

#define LVS(VRT,RA,RB)		lvsl	VRT,RA,RB

#define VPERM(VRT,VRA,VRB,VRC)	vperm	VRT,VRA,VRB,VRC
@@ -80,7 +85,6 @@ 




_GLOBAL(__copy_tofrom_user_power7)

#ifdef CONFIG_ALTIVEC

	cmpldi	r5,16

	cmpldi	cr1,r5,3328
@@ -89,15 +93,12 @@ _GLOBAL(__copy_tofrom_user_power7) 
	std	r5,-STACKFRAMESIZE+STK_REG(R29)(r1)



	blt	.Lshort_copy

	bge	cr1,.Lvmx_copy

#else

	cmpldi	r5,16



	std	r3,-STACKFRAMESIZE+STK_REG(R31)(r1)

	std	r4,-STACKFRAMESIZE+STK_REG(R30)(r1)

	std	r5,-STACKFRAMESIZE+STK_REG(R29)(r1)



	blt	.Lshort_copy

#ifdef CONFIG_ALTIVEC

test_feature = SELFTEST_CASE

BEGIN_FTR_SECTION

	bgt	cr1,.Lvmx_copy

END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)

#endif



.Lnonvmx_copy:
@@ -278,8 +279,8 @@ err1; stb r0,0(r3) 
	addi	r1,r1,STACKFRAMESIZE

	b	.Lnonvmx_copy



#ifdef CONFIG_ALTIVEC

.Lvmx_copy:

#ifdef CONFIG_ALTIVEC

	mflr	r0

	std	r0,16(r1)

	stdu	r1,-STACKFRAMESIZE(r1)

arch/powerpc/lib/memcpy_64.S

+7 −2
Original line number Diff line number Diff line
@@ -12,6 +12,11 @@ 
#include <asm/asm-compat.h>

#include <asm/feature-fixups.h>



#ifndef SELFTEST_CASE

/* For big-endian, 0 == most CPUs, 1 == POWER6, 2 == Cell */

#define SELFTEST_CASE	0

#endif



	.align	7

_GLOBAL_TOC(memcpy)

BEGIN_FTR_SECTION
@@ -22,10 +27,8 @@ BEGIN_FTR_SECTION 
#endif

FTR_SECTION_ELSE

#ifdef CONFIG_PPC_BOOK3S_64

#ifndef SELFTEST

	b	memcpy_power7

#endif

#endif

ALT_FTR_SECTION_END_IFCLR(CPU_FTR_VMX_COPY)

#ifdef __LITTLE_ENDIAN__

	/* dumb little-endian memcpy that will get replaced at runtime */
@@ -49,6 +52,7 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_VMX_COPY) 
   cleared.

   At the time of writing the only CPU that has this combination of bits

   set is Power6. */

test_feature = (SELFTEST_CASE == 1)

BEGIN_FTR_SECTION

	nop

FTR_SECTION_ELSE
@@ -57,6 +61,7 @@ ALT_FTR_SECTION_END(CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_CP_USE_DCBTZ, \ 
                    CPU_FTR_UNALIGNED_LD_STD)

.Ldst_aligned:

	addi	r3,r3,-16

test_feature = (SELFTEST_CASE == 0)

BEGIN_FTR_SECTION

	andi.	r0,r4,7

	bne	.Lsrc_unaligned

arch/powerpc/lib/memcpy_power7.S

+11 −11
Original line number Diff line number Diff line
@@ -19,7 +19,10 @@ 
 */

#include <asm/ppc_asm.h>



_GLOBAL(memcpy_power7)

#ifndef SELFTEST_CASE

/* 0 == don't use VMX, 1 == use VMX */

#define SELFTEST_CASE	0

#endif



#ifdef __BIG_ENDIAN__

#define LVS(VRT,RA,RB)		lvsl	VRT,RA,RB
@@ -29,20 +32,17 @@ _GLOBAL(memcpy_power7) 
#define VPERM(VRT,VRA,VRB,VRC)	vperm	VRT,VRB,VRA,VRC

#endif



#ifdef CONFIG_ALTIVEC

_GLOBAL(memcpy_power7)

	cmpldi	r5,16

	cmpldi	cr1,r5,4096



	std	r3,-STACKFRAMESIZE+STK_REG(R31)(r1)



	blt	.Lshort_copy

	bgt	cr1,.Lvmx_copy

#else

	cmpldi	r5,16



	std	r3,-STACKFRAMESIZE+STK_REG(R31)(r1)



	blt	.Lshort_copy

#ifdef CONFIG_ALTIVEC

test_feature = SELFTEST_CASE

BEGIN_FTR_SECTION

	bgt	cr1, .Lvmx_copy

END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)

#endif



.Lnonvmx_copy:
@@ -223,8 +223,8 @@ _GLOBAL(memcpy_power7) 
	addi	r1,r1,STACKFRAMESIZE

	b	.Lnonvmx_copy



#ifdef CONFIG_ALTIVEC

.Lvmx_copy:

#ifdef CONFIG_ALTIVEC

	mflr	r0

	std	r4,-STACKFRAMESIZE+STK_REG(R30)(r1)

	std	r5,-STACKFRAMESIZE+STK_REG(R29)(r1)

tools/testing/selftests/powerpc/copyloops/.gitignore

+10 −4
Original line number Diff line number Diff line 
copyuser_64

copyuser_power7

memcpy_64

memcpy_power7
 
copyuser_64_t0

copyuser_64_t1

copyuser_64_t2

copyuser_power7_t0

copyuser_power7_t1

memcpy_64_t0

memcpy_64_t1

memcpy_64_t2

memcpy_power7_t0

memcpy_power7_t1

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