perf vendor events amd: perf PMU events for AMD Family 17h (98c07a8f) · Commits · 戴 / test

tools/perf/pmu-events/arch/x86/amdfam17h/branch.json

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		[
		{
		"EventName": "bp_l1_btb_correct",
		"EventCode": "0x8a",
		"BriefDescription": "L1 BTB Correction."
		},
		{
		"EventName": "bp_l2_btb_correct",
		"EventCode": "0x8b",
		"BriefDescription": "L2 BTB Correction."
		}
		]

tools/perf/pmu-events/arch/x86/amdfam17h/cache.json

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		[
		{
		"EventName": "ic_fw32",
		"EventCode": "0x80",
		"BriefDescription": "The number of 32B fetch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill responses)."
		},
		{
		"EventName": "ic_fw32_miss",
		"EventCode": "0x81",
		"BriefDescription": "The number of 32B fetch windows tried to read the L1 IC and missed in the full tag."
		},
		{
		"EventName": "ic_cache_fill_l2",
		"EventCode": "0x82",
		"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
		},
		{
		"EventName": "ic_cache_fill_sys",
		"EventCode": "0x83",
		"BriefDescription": "The number of 64 byte instruction cache line fulfilled from system memory or another cache."
		},
		{
		"EventName": "bp_l1_tlb_miss_l2_hit",
		"EventCode": "0x84",
		"BriefDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
		},
		{
		"EventName": "bp_l1_tlb_miss_l2_miss",
		"EventCode": "0x85",
		"BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
		},
		{
		"EventName": "bp_snp_re_sync",
		"EventCode": "0x86",
		"BriefDescription": "The number of pipeline restarts caused by invalidating probes that hit on the instruction stream currently being executed. This would happen if the active instruction stream was being modified by another processor in an MP system - typically a highly unlikely event."
		},
		{
		"EventName": "ic_fetch_stall.ic_stall_any",
		"EventCode": "0x87",
		"BriefDescription": "IC pipe was stalled during this clock cycle for any reason (nothing valid in pipe ICM1).",
		"PublicDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle for any reason (nothing valid in pipe ICM1).",
		"UMask": "0x4"
		},
		{
		"EventName": "ic_fetch_stall.ic_stall_dq_empty",
		"EventCode": "0x87",
		"BriefDescription": "IC pipe was stalled during this clock cycle (including IC to OC fetches) due to DQ empty.",
		"PublicDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to DQ empty.",
		"UMask": "0x2"
		},
		{
		"EventName": "ic_fetch_stall.ic_stall_back_pressure",
		"EventCode": "0x87",
		"BriefDescription": "IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
		"PublicDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
		"UMask": "0x1"
		},
		{
		"EventName": "ic_cache_inval.l2_invalidating_probe",
		"EventCode": "0x8c",
		"BriefDescription": "IC line invalidated due to L2 invalidating probe (external or LS).",
		"PublicDescription": "The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core. IC line invalidated due to L2 invalidating probe (external or LS).",
		"UMask": "0x2"
		},
		{
		"EventName": "ic_cache_inval.fill_invalidated",
		"EventCode": "0x8c",
		"BriefDescription": "IC line invalidated due to overwriting fill response.",
		"PublicDescription": "The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core. IC line invalidated due to overwriting fill response.",
		"UMask": "0x1"
		},
		{
		"EventName": "bp_tlb_rel",
		"EventCode": "0x99",
		"BriefDescription": "The number of ITLB reload requests."
		},
		{
		"EventName": "l2_request_g1.rd_blk_l",
		"EventCode": "0x60",
		"BriefDescription": "Requests to L2 Group1.",
		"PublicDescription": "Requests to L2 Group1.",
		"UMask": "0x80"
		},
		{
		"EventName": "l2_request_g1.rd_blk_x",
		"EventCode": "0x60",
		"BriefDescription": "Requests to L2 Group1.",
		"PublicDescription": "Requests to L2 Group1.",
		"UMask": "0x40"
		},
		{
		"EventName": "l2_request_g1.ls_rd_blk_c_s",
		"EventCode": "0x60",
		"BriefDescription": "Requests to L2 Group1.",
		"PublicDescription": "Requests to L2 Group1.",
		"UMask": "0x20"
		},
		{
		"EventName": "l2_request_g1.cacheable_ic_read",
		"EventCode": "0x60",
		"BriefDescription": "Requests to L2 Group1.",
		"PublicDescription": "Requests to L2 Group1.",
		"UMask": "0x10"
		},
		{
		"EventName": "l2_request_g1.change_to_x",
		"EventCode": "0x60",
		"BriefDescription": "Requests to L2 Group1.",
		"PublicDescription": "Requests to L2 Group1.",
		"UMask": "0x8"
		},
		{
		"EventName": "l2_request_g1.prefetch_l2",
		"EventCode": "0x60",
		"BriefDescription": "Requests to L2 Group1.",
		"PublicDescription": "Requests to L2 Group1.",
		"UMask": "0x4"
		},
		{
		"EventName": "l2_request_g1.l2_hw_pf",
		"EventCode": "0x60",
		"BriefDescription": "Requests to L2 Group1.",
		"PublicDescription": "Requests to L2 Group1.",
		"UMask": "0x2"
		},
		{
		"EventName": "l2_request_g1.other_requests",
		"EventCode": "0x60",
		"BriefDescription": "Events covered by l2_request_g2.",
		"PublicDescription": "Requests to L2 Group1. Events covered by l2_request_g2.",
		"UMask": "0x1"
		},
		{
		"EventName": "l2_request_g2.group1",
		"EventCode": "0x61",
		"BriefDescription": "All Group 1 commands not in unit0.",
		"PublicDescription": "Multi-events in that LS and IF requests can be received simultaneous. All Group 1 commands not in unit0.",
		"UMask": "0x80"
		},
		{
		"EventName": "l2_request_g2.ls_rd_sized",
		"EventCode": "0x61",
		"BriefDescription": "RdSized, RdSized32, RdSized64.",
		"PublicDescription": "Multi-events in that LS and IF requests can be received simultaneous. RdSized, RdSized32, RdSized64.",
		"UMask": "0x40"
		},
		{
		"EventName": "l2_request_g2.ls_rd_sized_nc",
		"EventCode": "0x61",
		"BriefDescription": "RdSizedNC, RdSized32NC, RdSized64NC.",
		"PublicDescription": "Multi-events in that LS and IF requests can be received simultaneous. RdSizedNC, RdSized32NC, RdSized64NC.",
		"UMask": "0x20"
		},
		{
		"EventName": "l2_request_g2.ic_rd_sized",
		"EventCode": "0x61",
		"BriefDescription": "Multi-events in that LS and IF requests can be received simultaneous.",
		"PublicDescription": "Multi-events in that LS and IF requests can be received simultaneous.",
		"UMask": "0x10"
		},
		{
		"EventName": "l2_request_g2.ic_rd_sized_nc",
		"EventCode": "0x61",
		"BriefDescription": "Multi-events in that LS and IF requests can be received simultaneous.",
		"PublicDescription": "Multi-events in that LS and IF requests can be received simultaneous.",
		"UMask": "0x8"
		},
		{
		"EventName": "l2_request_g2.smc_inval",
		"EventCode": "0x61",
		"BriefDescription": "Multi-events in that LS and IF requests can be received simultaneous.",
		"PublicDescription": "Multi-events in that LS and IF requests can be received simultaneous.",
		"UMask": "0x4"
		},
		{
		"EventName": "l2_request_g2.bus_locks_originator",
		"EventCode": "0x61",
		"BriefDescription": "Multi-events in that LS and IF requests can be received simultaneous.",
		"PublicDescription": "Multi-events in that LS and IF requests can be received simultaneous.",
		"UMask": "0x2"
		},
		{
		"EventName": "l2_request_g2.bus_locks_responses",
		"EventCode": "0x61",
		"BriefDescription": "Multi-events in that LS and IF requests can be received simultaneous.",
		"PublicDescription": "Multi-events in that LS and IF requests can be received simultaneous.",
		"UMask": "0x1"
		},
		{
		"EventName": "l2_latency.l2_cycles_waiting_on_fills",
		"EventCode": "0x62",
		"BriefDescription": "Total cycles spent waiting for L2 fills to complete from L3 or memory, divided by four. Event counts are for both threads. To calculate average latency, the number of fills from both threads must be used.",
		"PublicDescription": "Total cycles spent waiting for L2 fills to complete from L3 or memory, divided by four. Event counts are for both threads. To calculate average latency, the number of fills from both threads must be used.",
		"UMask": "0x1"
		},
		{
		"EventName": "l2_wcb_req.wcb_write",
		"EventCode": "0x63",
		"PublicDescription": "LS (Load/Store unit) to L2 WCB (Write Combining Buffer) write requests.",
		"BriefDescription": "LS to L2 WCB write requests.",
		"UMask": "0x40"
		},
		{
		"EventName": "l2_wcb_req.wcb_close",
		"EventCode": "0x63",
		"BriefDescription": "LS to L2 WCB close requests.",
		"PublicDescription": "LS (Load/Store unit) to L2 WCB (Write Combining Buffer) close requests.",
		"UMask": "0x20"
		},
		{
		"EventName": "l2_wcb_req.zero_byte_store",
		"EventCode": "0x63",
		"BriefDescription": "LS to L2 WCB zero byte store requests.",
		"PublicDescription": "LS (Load/Store unit) to L2 WCB (Write Combining Buffer) zero byte store requests.",
		"UMask": "0x4"
		},
		{
		"EventName": "l2_wcb_req.cl_zero",
		"EventCode": "0x63",
		"PublicDescription": "LS to L2 WCB cache line zeroing requests.",
		"BriefDescription": "LS (Load/Store unit) to L2 WCB (Write Combining Buffer) cache line zeroing requests.",
		"UMask": "0x1"
		},
		{
		"EventName": "l2_cache_req_stat.ls_rd_blk_cs",
		"EventCode": "0x64",
		"BriefDescription": "LS ReadBlock C/S Hit.",
		"PublicDescription": "This event does not count accesses to the L2 cache by the L2 prefetcher, but it does count accesses by the L1 prefetcher. LS ReadBlock C/S Hit.",
		"UMask": "0x80"
		},
		{
		"EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_x",
		"EventCode": "0x64",
		"BriefDescription": "LS Read Block L Hit X.",
		"PublicDescription": "This event does not count accesses to the L2 cache by the L2 prefetcher, but it does count accesses by the L1 prefetcher. LS Read Block L Hit X.",
		"UMask": "0x40"
		},
		{
		"EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_s",
		"EventCode": "0x64",
		"BriefDescription": "LsRdBlkL Hit Shared.",
		"PublicDescription": "This event does not count accesses to the L2 cache by the L2 prefetcher, but it does count accesses by the L1 prefetcher. LsRdBlkL Hit Shared.",
		"UMask": "0x20"
		},
		{
		"EventName": "l2_cache_req_stat.ls_rd_blk_x",
		"EventCode": "0x64",
		"BriefDescription": "LsRdBlkX/ChgToX Hit X. Count RdBlkX finding Shared as a Miss.",
		"PublicDescription": "This event does not count accesses to the L2 cache by the L2 prefetcher, but it does count accesses by the L1 prefetcher. LsRdBlkX/ChgToX Hit X. Count RdBlkX finding Shared as a Miss.",
		"UMask": "0x10"
		},
		{
		"EventName": "l2_cache_req_stat.ls_rd_blk_c",
		"EventCode": "0x64",
		"BriefDescription": "LS Read Block C S L X Change to X Miss.",
		"PublicDescription": "This event does not count accesses to the L2 cache by the L2 prefetcher, but it does count accesses by the L1 prefetcher. LS Read Block C S L X Change to X Miss.",
		"UMask": "0x8"
		},
		{
		"EventName": "l2_cache_req_stat.ic_fill_hit_x",
		"EventCode": "0x64",
		"BriefDescription": "IC Fill Hit Exclusive Stale.",
		"PublicDescription": "This event does not count accesses to the L2 cache by the L2 prefetcher, but it does count accesses by the L1 prefetcher. IC Fill Hit Exclusive Stale.",
		"UMask": "0x4"
		},
		{
		"EventName": "l2_cache_req_stat.ic_fill_hit_s",
		"EventCode": "0x64",
		"BriefDescription": "IC Fill Hit Shared.",
		"PublicDescription": "This event does not count accesses to the L2 cache by the L2 prefetcher, but it does count accesses by the L1 prefetcher. IC Fill Hit Shared.",
		"UMask": "0x2"
		},
		{
		"EventName": "l2_cache_req_stat.ic_fill_miss",
		"EventCode": "0x64",
		"BriefDescription": "IC Fill Miss.",
		"PublicDescription": "This event does not count accesses to the L2 cache by the L2 prefetcher, but it does count accesses by the L1 prefetcher. IC Fill Miss.",
		"UMask": "0x1"
		},
		{
		"EventName": "l2_fill_pending.l2_fill_busy",
		"EventCode": "0x6d",
		"BriefDescription": "Total cycles spent with one or more fill requests in flight from L2.",
		"PublicDescription": "Total cycles spent with one or more fill requests in flight from L2.",
		"UMask": "0x1"
		}
		]

tools/perf/pmu-events/arch/x86/amdfam17h/core.json

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		[
		{
		"EventName": "ex_ret_instr",
		"EventCode": "0xc0",
		"BriefDescription": "Retired Instructions."
		},
		{
		"EventName": "ex_ret_cops",
		"EventCode": "0xc1",
		"BriefDescription": "Retired Uops.",
		"PublicDescription": "The number of uOps retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4."
		},
		{
		"EventName": "ex_ret_brn",
		"EventCode": "0xc2",
		"BriefDescription": "[Retired Branch Instructions.",
		"PublicDescription": "The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
		},
		{
		"EventName": "ex_ret_brn_misp",
		"EventCode": "0xc3",
		"BriefDescription": "Retired Branch Instructions Mispredicted.",
		"PublicDescription": "The number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts)."
		},
		{
		"EventName": "ex_ret_brn_tkn",
		"EventCode": "0xc4",
		"BriefDescription": "Retired Taken Branch Instructions.",
		"PublicDescription": "The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
		},
		{
		"EventName": "ex_ret_brn_tkn_misp",
		"EventCode": "0xc5",
		"BriefDescription": "Retired Taken Branch Instructions Mispredicted.",
		"PublicDescription": "The number of retired taken branch instructions that were mispredicted."
		},
		{
		"EventName": "ex_ret_brn_far",
		"EventCode": "0xc6",
		"BriefDescription": "Retired Far Control Transfers.",
		"PublicDescription": "The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction."
		},
		{
		"EventName": "ex_ret_brn_resync",
		"EventCode": "0xc7",
		"BriefDescription": "Retired Branch Resyncs.",
		"PublicDescription": "The number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rare."
		},
		{
		"EventName": "ex_ret_near_ret",
		"EventCode": "0xc8",
		"BriefDescription": "Retired Near Returns.",
		"PublicDescription": "The number of near return instructions (RET or RET Iw) retired."
		},
		{
		"EventName": "ex_ret_near_ret_mispred",
		"EventCode": "0xc9",
		"BriefDescription": "Retired Near Returns Mispredicted.",
		"PublicDescription": "The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction."
		},
		{
		"EventName": "ex_ret_brn_ind_misp",
		"EventCode": "0xca",
		"BriefDescription": "Retired Indirect Branch Instructions Mispredicted.",
		"PublicDescription": "Retired Indirect Branch Instructions Mispredicted."
		},
		{
		"EventName": "ex_ret_mmx_fp_instr.sse_instr",
		"EventCode": "0xcb",
		"BriefDescription": "SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
		"PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
		"UMask": "0x4"
		},
		{
		"EventName": "ex_ret_mmx_fp_instr.mmx_instr",
		"EventCode": "0xcb",
		"BriefDescription": "MMX instructions.",
		"PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructions.",
		"UMask": "0x2"
		},
		{
		"EventName": "ex_ret_mmx_fp_instr.x87_instr",
		"EventCode": "0xcb",
		"BriefDescription": "x87 instructions.",
		"PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructions.",
		"UMask": "0x1"
		},
		{
		"EventName": "ex_ret_cond",
		"EventCode": "0xd1",
		"BriefDescription": "Retired Conditional Branch Instructions."
		},
		{
		"EventName": "ex_ret_cond_misp",
		"EventCode": "0xd2",
		"BriefDescription": "Retired Conditional Branch Instructions Mispredicted."
		},
		{
		"EventName": "ex_div_busy",
		"EventCode": "0xd3",
		"BriefDescription": "Div Cycles Busy count."
		},
		{
		"EventName": "ex_div_count",
		"EventCode": "0xd4",
		"BriefDescription": "Div Op Count."
		},
		{
		"EventName": "ex_tagged_ibs_ops.ibs_count_rollover",
		"EventCode": "0x1cf",
		"BriefDescription": "Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.",
		"PublicDescription": "Tagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.",
		"UMask": "0x4"
		},
		{
		"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret",
		"EventCode": "0x1cf",
		"BriefDescription": "Number of Ops tagged by IBS that retired.",
		"PublicDescription": "Tagged IBS Ops. Number of Ops tagged by IBS that retired.",
		"UMask": "0x2"
		},
		{
		"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops",
		"EventCode": "0x1cf",
		"BriefDescription": "Number of Ops tagged by IBS.",
		"PublicDescription": "Tagged IBS Ops. Number of Ops tagged by IBS.",
		"UMask": "0x1"
		},
		{
		"EventName": "ex_ret_fus_brnch_inst",
		"EventCode": "0x1d0",
		"BriefDescription": "The number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3."
		}
		]

tools/perf/pmu-events/arch/x86/amdfam17h/floating-point.json

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tools/perf/pmu-events/arch/x86/amdfam17h/memory.json

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