Commit 98ba8e80 authored by Michael Ellerman's avatar Michael Ellerman
Browse files
Merge changes from Scott:
  Includes a couple of device tree fixes, a spelling fix, and leftover
  code cleanup.
parents 0695f8bc a76bea02
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+47 −5
Original line number Diff line number Diff line
@@ -210,13 +210,19 @@

		fman@400000 {
			ethernet@e0000 {
				fixed-link = <0 1 1000 0 0>;
				phy-connection-type = "sgmii";
				phy-mode = "sgmii";
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};

			ethernet@e2000 {
				fixed-link = <1 1 1000 0 0>;
				phy-connection-type = "sgmii";
				phy-mode = "sgmii";
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};

			ethernet@e4000 {
@@ -229,7 +235,7 @@

			ethernet@e8000 {
				phy-handle = <&front_phy>;
				phy-connection-type = "rgmii";
				phy-mode = "rgmii-id";
			};

			mdio0: mdio@fc000 {
@@ -258,14 +264,50 @@

	pci1: pcie@ffe250000 {
		status = "disabled";
		reg = <0xf 0xfe250000 0 0x10000>;
		ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000
			  0x01000000 0 0 0xf 0xf8010000 0 0x00010000>;
		pcie@0 {
			ranges = <0x02000000 0 0xe0000000
				  0x02000000 0 0xe0000000
				  0 0x10000000

				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00010000>;
		};
	};

	pci2: pcie@ffe260000 {
		status = "disabled";
		reg = <0xf 0xfe260000 0 0x10000>;
		ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
			  0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
		pcie@0 {
			ranges = <0x02000000 0 0xe0000000
				  0x02000000 0 0xe0000000
				  0 0x10000000

				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00010000>;
		};
	};

	pci3: pcie@ffe270000 {
		status = "disabled";
		reg = <0xf 0xfe270000 0 0x10000>;
		ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
			  0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
		pcie@0 {
			ranges = <0x02000000 0 0xe0000000
				  0x02000000 0 0xe0000000
				  0 0x10000000

				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00010000>;
		};
	};

	qe: qe@ffe140000 {
+1 −1
Original line number Diff line number Diff line
@@ -231,7 +231,7 @@ _GLOBAL(__setup_cpu_e5500)
	blr
#endif

/* flush L1 date cache, it can apply to e500v2, e500mc and e5500 */
/* flush L1 data cache, it can apply to e500v2, e500mc and e5500 */
_GLOBAL(flush_dcache_L1)
	mfmsr	r10
	wrteei	0
+0 −23
Original line number Diff line number Diff line
@@ -86,29 +86,6 @@ void __init mpc85xx_cpm2_pic_init(void)
#endif

#ifdef CONFIG_QUICC_ENGINE
void __init mpc85xx_qe_init(void)
{
	struct device_node *np;

	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
	if (!np) {
		np = of_find_node_by_name(NULL, "qe");
		if (!np) {
			pr_err("%s: Could not find Quicc Engine node\n",
					__func__);
			return;
		}
	}

	if (!of_device_is_available(np)) {
		of_node_put(np);
		return;
	}

	of_node_put(np);

}

void __init mpc85xx_qe_par_io_init(void)
{
	struct device_node *np;
+0 −2
Original line number Diff line number Diff line
@@ -66,8 +66,6 @@ void __init corenet_gen_setup_arch(void)
	swiotlb_detect_4g();

	pr_info("%s board\n", ppc_md.name);

	mpc85xx_qe_init();
}

static const struct of_device_id of_device_ids[] = {
+0 −2
Original line number Diff line number Diff line
@@ -10,10 +10,8 @@ static inline void __init mpc85xx_cpm2_pic_init(void) {}
#endif /* CONFIG_CPM2 */

#ifdef CONFIG_QUICC_ENGINE
extern void mpc85xx_qe_init(void);
extern void mpc85xx_qe_par_io_init(void);
#else
static inline void __init mpc85xx_qe_init(void) {}
static inline void __init mpc85xx_qe_par_io_init(void) {}
#endif

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