[media] arm64: dts: mediatek: Add MDP for MT8173 (989b292a) · Commits · 戴 / test

arch/arm64/boot/dts/mediatek/mt8173.dtsi

+84 −0

Original line number	Diff line number	Diff line
		@@ -41,6 +41,14 @@
		dpi0 = &dpi0;
		dsi0 = &dsi0;
		dsi1 = &dsi1;
		mdp_rdma0 = &mdp_rdma0;
		mdp_rdma1 = &mdp_rdma1;
		mdp_rsz0 = &mdp_rsz0;
		mdp_rsz1 = &mdp_rsz1;
		mdp_rsz2 = &mdp_rsz2;
		mdp_wdma0 = &mdp_wdma0;
		mdp_wrot0 = &mdp_wrot0;
		mdp_wrot1 = &mdp_wrot1;
		};

		cpus {
		@@ -755,6 +763,82 @@
		#clock-cells = <1>;
		};

		mdp {
		compatible = "mediatek,mt8173-mdp";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		mediatek,vpu = <&vpu>;

		mdp_rdma0: rdma@14001000 {
		compatible = "mediatek,mt8173-mdp-rdma";
		reg = <0 0x14001000 0 0x1000>;
		clocks = <&mmsys CLK_MM_MDP_RDMA0>,
		<&mmsys CLK_MM_MUTEX_32K>;
		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
		iommus = <&iommu M4U_PORT_MDP_RDMA0>;
		mediatek,larb = <&larb0>;
		};

		mdp_rdma1: rdma@14002000 {
		compatible = "mediatek,mt8173-mdp-rdma";
		reg = <0 0x14002000 0 0x1000>;
		clocks = <&mmsys CLK_MM_MDP_RDMA1>,
		<&mmsys CLK_MM_MUTEX_32K>;
		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
		iommus = <&iommu M4U_PORT_MDP_RDMA1>;
		mediatek,larb = <&larb4>;
		};

		mdp_rsz0: rsz@14003000 {
		compatible = "mediatek,mt8173-mdp-rsz";
		reg = <0 0x14003000 0 0x1000>;
		clocks = <&mmsys CLK_MM_MDP_RSZ0>;
		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
		};

		mdp_rsz1: rsz@14004000 {
		compatible = "mediatek,mt8173-mdp-rsz";
		reg = <0 0x14004000 0 0x1000>;
		clocks = <&mmsys CLK_MM_MDP_RSZ1>;
		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
		};

		mdp_rsz2: rsz@14005000 {
		compatible = "mediatek,mt8173-mdp-rsz";
		reg = <0 0x14005000 0 0x1000>;
		clocks = <&mmsys CLK_MM_MDP_RSZ2>;
		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
		};

		mdp_wdma0: wdma@14006000 {
		compatible = "mediatek,mt8173-mdp-wdma";
		reg = <0 0x14006000 0 0x1000>;
		clocks = <&mmsys CLK_MM_MDP_WDMA>;
		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
		iommus = <&iommu M4U_PORT_MDP_WDMA>;
		mediatek,larb = <&larb0>;
		};

		mdp_wrot0: wrot@14007000 {
		compatible = "mediatek,mt8173-mdp-wrot";
		reg = <0 0x14007000 0 0x1000>;
		clocks = <&mmsys CLK_MM_MDP_WROT0>;
		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
		iommus = <&iommu M4U_PORT_MDP_WROT0>;
		mediatek,larb = <&larb0>;
		};

		mdp_wrot1: wrot@14008000 {
		compatible = "mediatek,mt8173-mdp-wrot";
		reg = <0 0x14008000 0 0x1000>;
		clocks = <&mmsys CLK_MM_MDP_WROT1>;
		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
		iommus = <&iommu M4U_PORT_MDP_WROT1>;
		mediatek,larb = <&larb4>;
		};
		};

		ovl0: ovl@1400c000 {
		compatible = "mediatek,mt8173-disp-ovl";
		reg = <0 0x1400c000 0 0x1000>;

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