mt76x2u: align channel gain logic to mt76x2 one (989582e5) · Commits · 戴 / test

drivers/net/wireless/mediatek/mt76/mt76x2/dfs.h

+0 −1

Original line number	Diff line number	Diff line
		@@ -19,7 +19,6 @@

		void mt76x2_dfs_init_params(struct mt76x02_dev *dev);
		void mt76x2_dfs_init_detector(struct mt76x02_dev *dev);
		void mt76x2_dfs_adjust_agc(struct mt76x02_dev *dev);
		void mt76x2_dfs_set_domain(struct mt76x02_dev *dev,
		enum nl80211_dfs_regions region);

drivers/net/wireless/mediatek/mt76/mt76x2/mt76x2.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -98,5 +98,6 @@ void mt76x2_phy_set_txpower_regs(struct mt76x02_dev *dev,
		void mt76x2_configure_tx_delay(struct mt76x02_dev *dev,
		enum nl80211_band band, u8 bw);
		void mt76x2_apply_gain_adj(struct mt76x02_dev *dev);
		void mt76x2_phy_update_channel_gain(struct mt76x02_dev *dev);

		#endif

drivers/net/wireless/mediatek/mt76/mt76x2/mt76x2u.h

+0 −2

Original line number	Diff line number	Diff line
		@@ -46,8 +46,6 @@ void mt76x2u_phy_calibrate(struct work_struct *work);
		void mt76x2u_phy_channel_calibrate(struct mt76x02_dev *dev);

		void mt76x2u_mcu_complete_urb(struct urb *urb);
		int mt76x2u_mcu_set_dynamic_vga(struct mt76x02_dev *dev, u8 channel, bool ap,
		bool ext, int rssi, u32 false_cca);
		int mt76x2u_mcu_init(struct mt76x02_dev *dev);
		int mt76x2u_mcu_fw_init(struct mt76x02_dev *dev);

drivers/net/wireless/mediatek/mt76/mt76x2/pci_dfs.c

+0 −21

Original line number	Diff line number	Diff line
		@@ -803,27 +803,6 @@ static void mt76x2_dfs_set_bbp_params(struct mt76x02_dev *dev)
		mt76_wr(dev, 0x212c, 0x0c350001);
		}

		void mt76x2_dfs_adjust_agc(struct mt76x02_dev *dev)
		{
		u32 agc_r8, agc_r4, val_r8, val_r4, dfs_r31;

		agc_r8 = mt76_rr(dev, MT_BBP(AGC, 8));
		agc_r4 = mt76_rr(dev, MT_BBP(AGC, 4));

		val_r8 = (agc_r8 & 0x00007e00) >> 9;
		val_r4 = agc_r4 & ~0x1f000000;
		val_r4 += (((val_r8 + 1) >> 1) << 24);
		mt76_wr(dev, MT_BBP(AGC, 4), val_r4);

		dfs_r31 = FIELD_GET(MT_BBP_AGC_LNA_HIGH_GAIN, val_r4);
		dfs_r31 += val_r8;
		dfs_r31 -= (agc_r8 & 0x00000038) >> 3;
		dfs_r31 = (dfs_r31 << 16) \| 0x00000307;
		mt76_wr(dev, MT_BBP(DFS, 31), dfs_r31);

		mt76_wr(dev, MT_BBP(DFS, 32), 0x00040071);
		}

		void mt76x2_dfs_init_params(struct mt76x02_dev *dev)
		{
		struct cfg80211_chan_def *chandef = &dev->mt76.chandef;

drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c

+0 −90

Original line number	Diff line number	Diff line
		@@ -124,96 +124,6 @@ void mt76x2_phy_set_antenna(struct mt76x02_dev *dev)
		mt76_wr(dev, MT_BBP(AGC, 0), val);
		}

		static void
		mt76x2_phy_set_gain_val(struct mt76x02_dev *dev)
		{
		u32 val;
		u8 gain_val[2];

		gain_val[0] = dev->cal.agc_gain_cur[0] - dev->cal.agc_gain_adjust;
		gain_val[1] = dev->cal.agc_gain_cur[1] - dev->cal.agc_gain_adjust;

		if (dev->mt76.chandef.width >= NL80211_CHAN_WIDTH_40)
		val = 0x1e42 << 16;
		else
		val = 0x1836 << 16;

		val \|= 0xf8;

		mt76_wr(dev, MT_BBP(AGC, 8),
		val \| FIELD_PREP(MT_BBP_AGC_GAIN, gain_val[0]));
		mt76_wr(dev, MT_BBP(AGC, 9),
		val \| FIELD_PREP(MT_BBP_AGC_GAIN, gain_val[1]));

		if (dev->mt76.chandef.chan->flags & IEEE80211_CHAN_RADAR)
		mt76x2_dfs_adjust_agc(dev);
		}

		static void
		mt76x2_phy_update_channel_gain(struct mt76x02_dev *dev)
		{
		u8 *gain = dev->cal.agc_gain_init;
		u8 low_gain_delta, gain_delta;
		bool gain_change;
		int low_gain;
		u32 val;

		dev->cal.avg_rssi_all = mt76x02_phy_get_min_avg_rssi(dev);

		low_gain = (dev->cal.avg_rssi_all > mt76x02_get_rssi_gain_thresh(dev)) +
		(dev->cal.avg_rssi_all > mt76x02_get_low_rssi_gain_thresh(dev));

		gain_change = (dev->cal.low_gain & 2) ^ (low_gain & 2);
		dev->cal.low_gain = low_gain;

		if (!gain_change) {
		if (mt76x02_phy_adjust_vga_gain(dev))
		mt76x2_phy_set_gain_val(dev);
		return;
		}

		if (dev->mt76.chandef.width == NL80211_CHAN_WIDTH_80) {
		mt76_wr(dev, MT_BBP(RXO, 14), 0x00560211);
		val = mt76_rr(dev, MT_BBP(AGC, 26)) & ~0xf;
		if (low_gain == 2)
		val \|= 0x3;
		else
		val \|= 0x5;
		mt76_wr(dev, MT_BBP(AGC, 26), val);
		} else {
		mt76_wr(dev, MT_BBP(RXO, 14), 0x00560423);
		}

		if (mt76x2_has_ext_lna(dev))
		low_gain_delta = 10;
		else
		low_gain_delta = 14;

		if (low_gain == 2) {
		mt76_wr(dev, MT_BBP(RXO, 18), 0xf000a990);
		mt76_wr(dev, MT_BBP(AGC, 35), 0x08080808);
		mt76_wr(dev, MT_BBP(AGC, 37), 0x08080808);
		gain_delta = low_gain_delta;
		dev->cal.agc_gain_adjust = 0;
		} else {
		mt76_wr(dev, MT_BBP(RXO, 18), 0xf000a991);
		if (dev->mt76.chandef.width == NL80211_CHAN_WIDTH_80)
		mt76_wr(dev, MT_BBP(AGC, 35), 0x10101014);
		else
		mt76_wr(dev, MT_BBP(AGC, 35), 0x11111116);
		mt76_wr(dev, MT_BBP(AGC, 37), 0x2121262C);
		gain_delta = 0;
		dev->cal.agc_gain_adjust = low_gain_delta;
		}

		dev->cal.agc_gain_cur[0] = gain[0] - gain_delta;
		dev->cal.agc_gain_cur[1] = gain[1] - gain_delta;
		mt76x2_phy_set_gain_val(dev);

		/* clear false CCA counters */
		mt76_rr(dev, MT_RX_STAT_1);
		}

		int mt76x2_phy_set_channel(struct mt76x02_dev *dev,
		struct cfg80211_chan_def *chandef)
		{

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