Commit 98907c2d authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'DT-for-v3.15-part-1-v2' of git://git.stlinux.com/devel/kernel/linux-sti into next/dt 

Merge "STi DT changes part 1 v2" from Srinivas Kandagatla:

Patches : 01-02 are DT patches, adding interrupt support to pin
controller driver, Driver changes are already going via Linus W's
pinctrl tree.

Patches: 03 - 06 are DT patches for reset/softreset controller. Reset
controller driver is Acked by Philipp Zabel.

Patches: 07, 08 are DT patches, adding Ethernet controller support
patches, actual driver changes are already in v3.14-rc4 via Dave Millers
net tree.

Patches: 09, 10 are DT patches for IR driver support, actual IR driver
is already available since v3.12. Reason for the delay is due to
dependency on reset controller driver/headers.

* tag 'DT-for-v3.15-part-1-v2' of git://git.stlinux.com/devel/kernel/linux-sti

:
  ARM: STi: STIH416: Add IR support.
  ARM: STi: STIH415: Add IR support.
  ARM: STi: STiH416: Add ethernet support.
  ARM: STi: STiH415: Add ethernet support.
  ARM: STi: STiH416: Add soft reset controller support.
  ARM: STi: STiH416: Add reset controller support.
  ARM: STi: STiH415: Add soft reset controller support.
  ARM: STi: STiH415: Add reset controller support.
  ARM: STi: STiH415: Add interrupt support for pin controller
  ARM: STi: STiH416: Add interrupt support for pin controller

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 22261b22 e063735f

Documentation/devicetree/bindings/reset/st,sti-powerdown.txt

0 → 100644
+47 −0
Original line number Diff line number Diff line 
STMicroelectronics STi family Sysconfig Peripheral Powerdown Reset Controller

=============================================================================



This binding describes a reset controller device that is used to enable and

disable on-chip peripheral controllers such as USB and SATA, using

"powerdown" control bits found in the STi family SoC system configuration

registers. These have been grouped together into a single reset controller

device for convenience.



The actual action taken when powerdown is asserted is hardware dependent.

However, when asserted it may not be possible to access the hardware's

registers and after an assert/deassert sequence the hardware's previous state

may no longer be valid.



Please refer to reset.txt in this directory for common reset

controller binding usage.



Required properties:

- compatible: Should be "st,<chip>-powerdown"

	ex: "st,stih415-powerdown", "st,stih416-powerdown"

- #reset-cells: 1, see below



example:



	powerdown: powerdown-controller {

		#reset-cells = <1>;

		compatible = "st,stih415-powerdown";

	};





Specifying powerdown control of devices

=======================================



Device nodes should specify the reset channel required in their "resets"

property, containing a phandle to the powerdown device node and an

index specifying which channel to use, as described in reset.txt



example:



	usb1: usb@fe200000 {

		resets	= <&powerdown STIH41X_USB1_POWERDOWN>;

	};



Macro definitions for the supported reset channels can be found in:



include/dt-bindings/reset-controller/stih415-resets.h

include/dt-bindings/reset-controller/stih416-resets.h

Documentation/devicetree/bindings/reset/st,sti-softreset.txt

0 → 100644
+46 −0
Original line number Diff line number Diff line 
STMicroelectronics STi family Sysconfig Peripheral SoftReset Controller

=============================================================================



This binding describes a reset controller device that is used to enable and

disable on-chip peripheral controllers such as USB and SATA, using

"softreset" control bits found in the STi family SoC system configuration

registers.



The actual action taken when softreset is asserted is hardware dependent.

However, when asserted it may not be possible to access the hardware's

registers and after an assert/deassert sequence the hardware's previous state

may no longer be valid.



Please refer to reset.txt in this directory for common reset

controller binding usage.



Required properties:

- compatible: Should be "st,<chip>-softreset" example:

	"st,stih415-softreset" or "st,stih416-softreset";

- #reset-cells: 1, see below



example:



	softreset: softreset-controller {

		#reset-cells = <1>;

		compatible = "st,stih415-softreset";

	};





Specifying softreset control of devices

=======================================



Device nodes should specify the reset channel required in their "resets"

property, containing a phandle to the softreset device node and an

index specifying which channel to use, as described in reset.txt



example:



	ethernet0{

		resets			= <&softreset STIH415_ETH0_SOFTRESET>;

	};



Macro definitions for the supported reset channels can be found in:



include/dt-bindings/reset-controller/stih415-resets.h

include/dt-bindings/reset-controller/stih416-resets.h

arch/arm/boot/dts/stih415-clock.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -34,5 +34,19 @@ 
			compatible = "fixed-clock";

			clock-frequency = <100000000>;

		};



		CLKS_GMAC0_PHY: clockgenA1@7 {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <25000000>;

			clock-output-names = "CLKS_GMAC0_PHY";

		};



		CLKS_ETH1_PHY: clockgenA0@7 {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <25000000>;

			clock-output-names = "CLKS_ETH1_PHY";

		};

	};

};

arch/arm/boot/dts/stih415-pinctrl.dtsi

+204 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
 * publishhed by the Free Software Foundation.

 */

#include "st-pincfg.h"

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {



	aliases {
@@ -45,35 +46,49 @@ 
			#size-cells	= <1>;

			compatible	= "st,stih415-sbc-pinctrl";

			st,syscfg	= <&syscfg_sbc>;

			reg 		= <0xfe61f080 0x4>;

			reg-names	= "irqmux";

			interrupts 	= <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;

			interrupts-names = "irqmux";

			ranges 		= <0 0xfe610000 0x5000>;



			PIO0: gpio@fe610000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0 0x100>;

				st,bank-name	= "PIO0";

			};

			PIO1: gpio@fe611000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x1000 0x100>;

				st,bank-name	= "PIO1";

			};

			PIO2: gpio@fe612000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x2000 0x100>;

				st,bank-name	= "PIO2";

			};

			PIO3: gpio@fe613000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x3000 0x100>;

				st,bank-name	= "PIO3";

			};

			PIO4: gpio@fe614000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x4000 0x100>;

				st,bank-name	= "PIO4";

			};
@@ -104,6 +119,64 @@ 
					};

				};

			};



			rc{

				pinctrl_ir: ir0 {

					st,pins {

						ir = <&PIO4 0 ALT2 IN>;

					};

				};

			};



			gmac1 {

				pinctrl_mii1: mii1 {

						st,pins {

						 txd0   = <&PIO0 0 ALT1 OUT  SE_NICLK_IO	0	CLK_A>;

						 txd1   = <&PIO0 1 ALT1 OUT  SE_NICLK_IO	0	CLK_A>;

						 txd2   = <&PIO0 2 ALT1 OUT  SE_NICLK_IO	0	CLK_A>;

						 txd3   = <&PIO0 3 ALT1 OUT  SE_NICLK_IO	0	CLK_A>;

						 txer   = <&PIO0 4 ALT1 OUT  SE_NICLK_IO	0	CLK_A>;

						 txen   = <&PIO0 5 ALT1 OUT  SE_NICLK_IO	0	CLK_A>;

						 txclk  = <&PIO0 6 ALT1 IN   NICLK	0	CLK_A>;

						 col    = <&PIO0 7 ALT1 IN   BYPASS	1000>;

						 mdio   = <&PIO1 0 ALT1 OUT  BYPASS	0>;

						 mdc    = <&PIO1 1 ALT1 OUT  NICLK	0	CLK_A>;

						 crs    = <&PIO1 2 ALT1 IN   BYPASS	1000>;

						 mdint  = <&PIO1 3 ALT1 IN   BYPASS	0>;

						 rxd0   = <&PIO1 4 ALT1 IN   SE_NICLK_IO	0	CLK_A>;

						 rxd1   = <&PIO1 5 ALT1 IN   SE_NICLK_IO	0	CLK_A>;

						 rxd2   = <&PIO1 6 ALT1 IN   SE_NICLK_IO	0	CLK_A>;

						 rxd3   = <&PIO1 7 ALT1 IN   SE_NICLK_IO	0	CLK_A>;

						 rxdv   = <&PIO2 0 ALT1 IN   SE_NICLK_IO	0	CLK_A>;

						 rx_er  = <&PIO2 1 ALT1 IN   SE_NICLK_IO	0	CLK_A>;

						 rxclk  = <&PIO2 2 ALT1 IN   NICLK	0	CLK_A>;

						 phyclk = <&PIO2 3 ALT1 IN   NICLK	1000	CLK_A>;

					};

				};



				pinctrl_rgmii1: rgmii1-0 {

					st,pins {

						 txd0 =	 <&PIO0 0 ALT1 OUT DE_IO	1000	CLK_A>;

						 txd1 =	 <&PIO0 1 ALT1 OUT DE_IO	1000	CLK_A>;

						 txd2 =	 <&PIO0 2 ALT1 OUT DE_IO	1000	CLK_A>;

						 txd3 =	 <&PIO0 3 ALT1 OUT DE_IO	1000	CLK_A>;

						 txen =	 <&PIO0 5 ALT1 OUT DE_IO	0	CLK_A>;

						 txclk = <&PIO0 6 ALT1 IN	NICLK	0	CLK_A>;

						 mdio =	 <&PIO1 0 ALT1 OUT	BYPASS	0>;

						 mdc =	 <&PIO1 1 ALT1 OUT	NICLK	0	CLK_A>;

						 rxd0 =	 <&PIO1 4 ALT1 IN DE_IO	0	CLK_A>;

						 rxd1 =	 <&PIO1 5 ALT1 IN DE_IO	0	CLK_A>;

						 rxd2 =	 <&PIO1 6 ALT1 IN DE_IO	0	CLK_A>;

						 rxd3 =	 <&PIO1 7 ALT1 IN DE_IO	0	CLK_A>;



						 rxdv =	  <&PIO2 0 ALT1 IN DE_IO	500	CLK_A>;

						 rxclk =  <&PIO2 2 ALT1 IN	NICLK	0	CLK_A>;

						 phyclk = <&PIO2 3 ALT4 OUT	NICLK	0	CLK_B>;



						 clk125= <&PIO3 7 ALT4 IN 	NICLK	0	CLK_A>;

					};

				};

			};

		};



		pin-controller-front {
@@ -111,53 +184,73 @@ 
			#size-cells	= <1>;

			compatible	= "st,stih415-front-pinctrl";

			st,syscfg	= <&syscfg_front>;

			reg 		= <0xfee0f080 0x4>;

			reg-names	= "irqmux";

			interrupts 	= <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;

			interrupts-names = "irqmux";

			ranges		= <0 0xfee00000 0x8000>;



			PIO5: gpio@fee00000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0 0x100>;

				st,bank-name	= "PIO5";

			};

			PIO6: gpio@fee01000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x1000 0x100>;

				st,bank-name	= "PIO6";

			};

			PIO7: gpio@fee02000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x2000 0x100>;

				st,bank-name	= "PIO7";

			};

			PIO8: gpio@fee03000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x3000 0x100>;

				st,bank-name	= "PIO8";

			};

			PIO9: gpio@fee04000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x4000 0x100>;

				st,bank-name	= "PIO9";

			};

			PIO10: gpio@fee05000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x5000 0x100>;

				st,bank-name	= "PIO10";

			};

			PIO11: gpio@fee06000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x6000 0x100>;

				st,bank-name	= "PIO11";

			};

			PIO12: gpio@fee07000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x7000 0x100>;

				st,bank-name	= "PIO12";

			};
@@ -186,41 +279,57 @@ 
			#size-cells	= <1>;

			compatible	= "st,stih415-rear-pinctrl";

			st,syscfg	= <&syscfg_rear>;

			reg 		= <0xfe82f080 0x4>;

			reg-names	= "irqmux";

			interrupts 	= <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;

			interrupts-names = "irqmux";

			ranges		= <0 0xfe820000 0x8000>;



			PIO13: gpio@fe820000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0 0x100>;

				st,bank-name	= "PIO13";

			};

			PIO14: gpio@fe821000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x1000 0x100>;

				st,bank-name	= "PIO14";

			};

			PIO15: gpio@fe822000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x2000 0x100>;

				st,bank-name	= "PIO15";

			};

			PIO16: gpio@fe823000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x3000 0x100>;

				st,bank-name	= "PIO16";

			};

			PIO17: gpio@fe824000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x4000 0x100>;

				st,bank-name	= "PIO17";

			};

			PIO18: gpio@fe825000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x5000 0x100>;

				st,bank-name	= "PIO18";

			};
@@ -233,6 +342,77 @@ 
					};

				};

			};



			gmac0{

				pinctrl_mii0: mii0 {

					st,pins {

					 mdint =	<&PIO13 6 ALT2	IN	BYPASS		0>;

					 txen =		<&PIO13 7 ALT2	OUT	SE_NICLK_IO	0	CLK_A>;



					 txd0 =		<&PIO14 0 ALT2	OUT	SE_NICLK_IO	0	CLK_A>;

					 txd1 =		<&PIO14 1 ALT2	OUT	SE_NICLK_IO	0	CLK_A>;

					 txd2 =		<&PIO14 2 ALT2	OUT	SE_NICLK_IO	0	CLK_B>;

					 txd3 =		<&PIO14 3 ALT2	OUT	SE_NICLK_IO	0	CLK_B>;



					 txclk =	<&PIO15 0 ALT2	IN	NICLK		0	CLK_A>;

					 txer =		<&PIO15 1 ALT2	OUT	SE_NICLK_IO	0	CLK_A>;

					 crs =		<&PIO15 2 ALT2	IN	BYPASS		1000>;

					 col =		<&PIO15 3 ALT2	IN	BYPASS		1000>;

					 mdio  =        <&PIO15 4 ALT2	OUT	BYPASS 	3000>;

					 mdc   =        <&PIO15 5 ALT2	OUT     NICLK  	0    	CLK_B>;



					 rxd0 =		<&PIO16 0 ALT2	IN	SE_NICLK_IO	0	CLK_A>;

					 rxd1 =		<&PIO16 1 ALT2	IN	SE_NICLK_IO	0	CLK_A>;

					 rxd2 =		<&PIO16 2 ALT2	IN	SE_NICLK_IO	0	CLK_A>;

					 rxd3 =		<&PIO16 3 ALT2	IN	SE_NICLK_IO	0	CLK_A>;

					 rxdv =		<&PIO15 6 ALT2	IN	SE_NICLK_IO	0	CLK_A>;

					 rx_er =	<&PIO15 7 ALT2	IN	SE_NICLK_IO	0	CLK_A>;

					 rxclk =	<&PIO17 0 ALT2	IN	NICLK		0	CLK_A>;

					 phyclk =	<&PIO13 5 ALT2	OUT	NICLK	1000	CLK_A>;



					};

				};



			pinctrl_gmii0: gmii0 {

				st,pins {

					 mdint =	<&PIO13 6	ALT2 IN		BYPASS	0>;

					 mdio  =        <&PIO15 4 	ALT2 OUT	BYPASS 	3000>;

					 mdc   =        <&PIO15 5 	ALT2 OUT    	NICLK  	0    	CLK_B>;

					 txen =		<&PIO13 7	ALT2 OUT	SE_NICLK_IO	3000	CLK_A>;



					 txd0 =		<&PIO14 0	ALT2 OUT	SE_NICLK_IO	3000	CLK_A>;

					 txd1 =		<&PIO14 1	ALT2 OUT	SE_NICLK_IO	3000	CLK_A>;

					 txd2 =		<&PIO14 2	ALT2 OUT	SE_NICLK_IO	3000	CLK_B>;

					 txd3 =		<&PIO14 3	ALT2 OUT	SE_NICLK_IO	3000	CLK_B>;

					 txd4 =		<&PIO14 4	ALT2 OUT	SE_NICLK_IO	3000	CLK_B>;

					 txd5 =		<&PIO14 5	ALT2 OUT	SE_NICLK_IO	3000	CLK_B>;

					 txd6 =		<&PIO14 6	ALT2 OUT	SE_NICLK_IO	3000	CLK_B>;

					 txd7 =		<&PIO14 7	ALT2 OUT	SE_NICLK_IO	3000	CLK_B>;



					 txclk =	<&PIO15 0	ALT2 IN		NICLK	0	CLK_A>;

					 txer =		<&PIO15 1	ALT2 OUT 	SE_NICLK_IO	3000	CLK_A>;

					 crs =		<&PIO15 2	ALT2 IN		BYPASS	1000>;

					 col =		<&PIO15 3	ALT2 IN		BYPASS	1000>;

					 rxdv =		<&PIO15 6	ALT2 IN		SE_NICLK_IO	1500	CLK_A>;

					 rx_er =	<&PIO15 7	ALT2 IN		SE_NICLK_IO	1500	CLK_A>;



					 rxd0 =		<&PIO16 0	ALT2 IN		SE_NICLK_IO	1500	CLK_A>;

					 rxd1 =		<&PIO16 1	ALT2 IN		SE_NICLK_IO	1500	CLK_A>;

					 rxd2 =		<&PIO16 2	ALT2 IN		SE_NICLK_IO	1500	CLK_A>;

					 rxd3 =		<&PIO16 3	ALT2 IN		SE_NICLK_IO	1500	CLK_A>;

					 rxd4 =		<&PIO16 4	ALT2 IN		SE_NICLK_IO	1500	CLK_A>;

					 rxd5 =		<&PIO16 5	ALT2 IN		SE_NICLK_IO	1500	CLK_A>;

					 rxd6 =		<&PIO16 6	ALT2 IN		SE_NICLK_IO	1500	CLK_A>;

					 rxd7 =		<&PIO16 7	ALT2 IN		SE_NICLK_IO	1500	CLK_A>;



					 rxclk =	<&PIO17 0	ALT2 IN	NICLK	0	CLK_A>;

					 clk125 =	<&PIO17 6	ALT1 IN	NICLK	0	CLK_A>;

                                         phyclk =       <&PIO13 5       ALT4 OUT NICLK   0       CLK_B>;





					};

				};

			};

		};



		pin-controller-left {
@@ -240,23 +420,33 @@ 
			#size-cells	= <1>;

			compatible	= "st,stih415-left-pinctrl";

			st,syscfg	= <&syscfg_left>;

			reg 		= <0xfd6bf080 0x4>;

			reg-names	= "irqmux";

			interrupts 	= <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;

			interrupts-names = "irqmux";

			ranges		= <0 0xfd6b0000 0x3000>;



			PIO100: gpio@fd6b0000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0 0x100>;

				st,bank-name	= "PIO100";

			};

			PIO101: gpio@fd6b1000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x1000 0x100>;

				st,bank-name	= "PIO101";

			};

			PIO102: gpio@fd6b2000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x2000 0x100>;

				st,bank-name	= "PIO102";

			};
@@ -267,35 +457,49 @@ 
			#size-cells	= <1>;

			compatible	= "st,stih415-right-pinctrl";

			st,syscfg	= <&syscfg_right>;

			reg 		= <0xfd33f080 0x4>;

			reg-names	= "irqmux";

			interrupts 	= <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;

			interrupts-names = "irqmux";

			ranges		= <0 0xfd330000 0x5000>;



			PIO103: gpio@fd330000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0 0x100>;

				st,bank-name	= "PIO103";

			};

			PIO104: gpio@fd331000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x1000 0x100>;

				st,bank-name	= "PIO104";

			};

			PIO105: gpio@fd332000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x2000 0x100>;

				st,bank-name	= "PIO105";

			};

			PIO106: gpio@fd333000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x3000 0x100>;

				st,bank-name	= "PIO106";

			};

			PIO107: gpio@fd334000 {

				gpio-controller;

				#gpio-cells	= <1>;

				interrupt-controller;

				#interrupt-cells = <2>;

				reg		= <0x4000 0x100>;

				st,bank-name	= "PIO107";

			};

arch/arm/boot/dts/stih415.dtsi

+70 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
#include "stih415-clock.dtsi"

#include "stih415-pinctrl.dtsi"

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/reset-controller/stih415-resets.h>

/ {



	L2: cache-controller {
@@ -28,6 +29,16 @@ 
		ranges;

		compatible	= "simple-bus";



		powerdown: powerdown-controller {

			#reset-cells = <1>;

			compatible = "st,stih415-powerdown";

		};



		softreset: softreset-controller {

			#reset-cells = <1>;

			compatible = "st,stih415-softreset";

		};



		syscfg_sbc: sbc-syscfg@fe600000{

			compatible      = "st,stih415-sbc-syscfg", "syscon";

			reg		= <0xfe600000 0xb4>;
@@ -136,5 +147,64 @@ 


			status		= "disabled";

		};



		ethernet0: dwmac@fe810000 {

			device_type 	= "network";

			compatible	= "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";

			status 		= "disabled";



			reg 		= <0xfe810000 0x8000>, <0x148 0x4>;

			reg-names	= "stmmaceth", "sti-ethconf";



			interrupts 	= <0 147 0>, <0 148 0>, <0 149 0>;

			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";

			resets			= <&softreset STIH415_ETH0_SOFTRESET>;

			reset-names		= "stmmaceth";



			snps,pbl 	= <32>;

			snps,mixed-burst;

			snps,force_sf_dma_mode;



			st,syscon	= <&syscfg_rear>;



			pinctrl-names 	= "default";

			pinctrl-0	= <&pinctrl_mii0>;

			clock-names	= "stmmaceth";

			clocks		= <&CLKS_GMAC0_PHY>;

		};



		ethernet1: dwmac@fef08000 {

			device_type = "network";

			compatible	= "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";

			status 		= "disabled";

			reg		= <0xfef08000 0x8000>, <0x74 0x4>;

			reg-names	= "stmmaceth", "sti-ethconf";

			interrupts 	= <0 150 0>, <0 151 0>, <0 152 0>;

			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";



			snps,pbl	= <32>;

			snps,mixed-burst;

			snps,force_sf_dma_mode;



			st,syscon		= <&syscfg_sbc>;



			resets			= <&softreset STIH415_ETH1_SOFTRESET>;

			reset-names		= "stmmaceth";

			pinctrl-names 	= "default";

			pinctrl-0	= <&pinctrl_mii1>;

			clock-names	= "stmmaceth";

			clocks		= <&CLKS_ETH1_PHY>;

		};



		rc: rc@fe518000 {

			compatible	= "st,comms-irb";

			reg		= <0xfe518000 0x234>;

			interrupts	=  <0 203 0>;

			clocks		= <&CLK_SYSIN>;

			rx-mode		= "infrared";

			pinctrl-names 	= "default";

			pinctrl-0	= <&pinctrl_ir>;

			resets		= <&softreset STIH415_IRB_SOFTRESET>;

		};

	};

};

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