drm/amdgpu: Add GPU reset functionality for Vega10 (98512bb8) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -2581,7 +2581,8 @@ static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
		if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) \|\|
		(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) \|\|
		(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) \|\|
		(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) {
		(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) \|\|
		adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
		if (adev->ip_blocks[i].status.hang) {
		DRM_INFO("Some block need full reset!\n");
		return true;

+20 −1

Original line number	Diff line number	Diff line
		@@ -62,6 +62,7 @@ static int psp_sw_init(void *handle)
		psp->cmd_submit = psp_v3_1_cmd_submit;
		psp->compare_sram_data = psp_v3_1_compare_sram_data;
		psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
		psp->mode1_reset = psp_v3_1_mode1_reset;
		break;
		case CHIP_RAVEN:
		psp->init_microcode = psp_v10_0_init_microcode;
		@@ -72,6 +73,7 @@ static int psp_sw_init(void *handle)
		psp->ring_destroy = psp_v10_0_ring_destroy;
		psp->cmd_submit = psp_v10_0_cmd_submit;
		psp->compare_sram_data = psp_v10_0_compare_sram_data;
		psp->mode1_reset = psp_v10_0_mode1_reset;
		break;
		default:
		return -EINVAL;
		@@ -497,6 +499,22 @@ failed:
		return ret;
		}

		static bool psp_check_reset(void* handle)
		{
		struct amdgpu_device adev = (struct amdgpu_device )handle;

		if (adev->flags & AMD_IS_APU)
		return true;

		return false;
		}

		static int psp_reset(void* handle)
		{
		struct amdgpu_device adev = (struct amdgpu_device )handle;
		return psp_mode1_reset(&adev->psp);
		}

		static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
		enum AMDGPU_UCODE_ID ucode_type)
		{
		@@ -540,8 +558,9 @@ const struct amd_ip_funcs psp_ip_funcs = {
		.suspend = psp_suspend,
		.resume = psp_resume,
		.is_idle = NULL,
		.check_soft_reset = psp_check_reset,
		.wait_for_idle = NULL,
		.soft_reset = NULL,
		.soft_reset = psp_reset,
		.set_clockgating_state = psp_set_clockgating_state,
		.set_powergating_state = psp_set_powergating_state,
		};

+3 −0

Original line number	Diff line number	Diff line
		@@ -76,6 +76,7 @@ struct psp_context
		struct amdgpu_firmware_info *ucode,
		enum AMDGPU_UCODE_ID ucode_type);
		bool (smu_reload_quirk)(struct psp_context psp);
		int (mode1_reset)(struct psp_context psp);

		/* fence buffer */
		struct amdgpu_bo *fw_pri_bo;
		@@ -139,6 +140,8 @@ struct amdgpu_psp_funcs {
		((psp)->bootloader_load_sos ? (psp)->bootloader_load_sos((psp)) : 0)
		#define psp_smu_reload_quirk(psp) \
		((psp)->smu_reload_quirk ? (psp)->smu_reload_quirk((psp)) : false)
		#define psp_mode1_reset(psp) \
		((psp)->mode1_reset ? (psp)->mode1_reset((psp)) : false)

		extern const struct amd_ip_funcs psp_ip_funcs;

+7 −0

Original line number	Diff line number	Diff line
		@@ -407,3 +407,10 @@ bool psp_v10_0_compare_sram_data(struct psp_context *psp,

		return true;
		}


		int psp_v10_0_mode1_reset(struct psp_context *psp)
		{
		DRM_INFO("psp mode 1 reset not supported now! \n");
		return -EINVAL;
		}

+2 −0

Original line number	Diff line number	Diff line
		@@ -45,4 +45,6 @@ extern int psp_v10_0_cmd_submit(struct psp_context *psp,
		extern bool psp_v10_0_compare_sram_data(struct psp_context *psp,
		struct amdgpu_firmware_info *ucode,
		enum AMDGPU_UCODE_ID ucode_type);

		extern int psp_v10_0_mode1_reset(struct psp_context *psp);
		#endif