Commit 9841c79c authored by Scott Wood's avatar Scott Wood
Browse files

powerpc/booke64: Guard e6500 tlb handler with CONFIG_PPC_FSL_BOOK3E 



...and make CONFIG_PPC_FSL_BOOK3E conflict with CONFIG_PPC_64K_PAGES.

This fixes a build break with CONFIG_PPC_64K_PAGES on 64-bit book3e,
that was introduced by commit 28efc35f
("powerpc/e6500: TLB miss handler with hardware tablewalk support").

Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
parent fac515db

arch/powerpc/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -526,6 +526,7 @@ config PPC_16K_PAGES 


config PPC_64K_PAGES

	bool "64k page size" if 44x || PPC_STD_MMU_64 || PPC_BOOK3E_64

	depends on !PPC_FSL_BOOK3E

	select PPC_HAS_HASH_64K if PPC_STD_MMU_64



config PPC_256K_PAGES

arch/powerpc/mm/tlb_low_64e.S

+2 −1
Original line number Diff line number Diff line
@@ -240,6 +240,7 @@ itlb_miss_fault_bolted: 
	beq	tlb_miss_common_bolted

	b	itlb_miss_kernel_bolted



#ifdef CONFIG_PPC_FSL_BOOK3E

/*

 * TLB miss handling for e6500 and derivatives, using hardware tablewalk.

 *
@@ -409,7 +410,7 @@ itlb_miss_fault_e6500: 
	TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)

	tlb_epilog_bolted

	b	exc_instruction_storage_book3e



#endif /* CONFIG_PPC_FSL_BOOK3E */



/**********************************************************************

 *                                                                    *

arch/powerpc/mm/tlb_nohash.c

+2 −0
Original line number Diff line number Diff line
@@ -557,10 +557,12 @@ static void setup_mmu_htw(void) 
		patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e);

		patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e);

		break;

#ifdef CONFIG_PPC_FSL_BOOK3E

	case PPC_HTW_E6500:

		patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e);

		patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e);

		break;

#endif

	}

	pr_info("MMU: Book3E HW tablewalk %s\n",

		book3e_htw_mode != PPC_HTW_NONE ? "enabled" : "not supported");

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