Commit 98339495 authored by Noam Camus's avatar Noam Camus Committed by Vineet Gupta
Browse files

ARC: [plat-eznps] Handle user memory error same in simulation and silicon 



On ARC700 (and nSIM), user mode memory error triggers an L2 interrupt
which is handled gracefully by kernel (or it tries to despite this being
imprecise, and error could get charged to kernel itself). The offending
task is killed and kernel moves on.

NPS hardware however raises a Machine Check exception for same error
which is NOT recoverable by kernel.

This patch aligns kernel handling for nSIM case, to same as hardware by
overriding the default user space bus error handler.

Signed-off-by: default avatarNoam Camus <noamca@mellanox.com>
Signed-off-by: default avatarElad Kanfi <eladkan@mellanox.com>
[vgupta: rewrote changelog]
Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent 644fa02b

arch/arc/kernel/traps.c

+1 −1
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ int name(unsigned long address, struct pt_regs *regs) \ 
DO_ERROR_INFO(SIGILL, "Priv Op/Disabled Extn", do_privilege_fault, ILL_PRVOPC)

DO_ERROR_INFO(SIGILL, "Invalid Extn Insn", do_extension_fault, ILL_ILLOPC)

DO_ERROR_INFO(SIGILL, "Illegal Insn (or Seq)", insterror_is_error, ILL_ILLOPC)

DO_ERROR_INFO(SIGBUS, "Invalid Mem Access", do_memory_error, BUS_ADRERR)

DO_ERROR_INFO(SIGBUS, "Invalid Mem Access", __weak do_memory_error, BUS_ADRERR)

DO_ERROR_INFO(SIGTRAP, "Breakpoint Set", trap_is_brkpt, TRAP_BRKPT)

DO_ERROR_INFO(SIGBUS, "Misaligned Access", do_misaligned_error, BUS_ADRALN)

arch/arc/plat-eznps/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -32,3 +32,14 @@ config EZNPS_MTM_EXT 
	  any of them seem like CPU from Linux point of view.

	  All threads within same core share the execution unit of the

	  core and HW scheduler round robin between them.



config EZNPS_MEM_ERROR_ALIGN

       bool "ARC-EZchip Memory error as an exception"

       depends on EZNPS_MTM_EXT

       default n

       help

	  On the real chip of the NPS, user memory errors are handled

	  as a machine check exception, which is fatal, whereas on

	  simulator platform for NPS, is handled as a Level 2 interrupt

	  (just a stock ARC700) which is recoverable. This option makes

	  simulator behave like hardware.

arch/arc/plat-eznps/mtm.c

+9 −0
Original line number Diff line number Diff line
@@ -25,6 +25,15 @@ 
#define MT_CTRL_ST_CNT		0xF

#define NPS_NUM_HW_THREADS	0x10



#ifdef CONFIG_EZNPS_MEM_ERROR_ALIGN

int do_memory_error(unsigned long address, struct pt_regs *regs)

{

	die("Invalid Mem Access", regs, address);



	return 1;

}

#endif



static void mtm_init_nat(int cpu)

{

	struct nps_host_reg_mtm_cfg mtm_cfg;

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