Commit 97ff4ca4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'char-misc-5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc 

Pull char / misc driver updates from Greg KH:
 "Here is the "large" pull request for char and misc and other assorted
  smaller driver subsystems for 5.3-rc1.

  It seems that this tree is becoming the funnel point of lots of
  smaller driver subsystems, which is fine for me, but that's why it is
  getting larger over time and does not just contain stuff under
  drivers/char/ and drivers/misc.

  Lots of small updates all over the place here from different driver
  subsystems:
   - habana driver updates
   - coresight driver updates
   - documentation file movements and updates
   - Android binder fixes and updates
   - extcon driver updates
   - google firmware driver updates
   - fsi driver updates
   - smaller misc and char driver updates
   - soundwire driver updates
   - nvmem driver updates
   - w1 driver fixes

  All of these have been in linux-next for a while with no reported
  issues"

* tag 'char-misc-5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (188 commits)
  coresight: Do not default to CPU0 for missing CPU phandle
  dt-bindings: coresight: Change CPU phandle to required property
  ocxl: Allow contexts to be attached with a NULL mm
  fsi: sbefifo: Don't fail operations when in SBE IPL state
  coresight: tmc: Smatch: Fix potential NULL pointer dereference
  coresight: etm3x: Smatch: Fix potential NULL pointer dereference
  coresight: Potential uninitialized variable in probe()
  coresight: etb10: Do not call smp_processor_id from preemptible
  coresight: tmc-etf: Do not call smp_processor_id from preemptible
  coresight: tmc-etr: alloc_perf_buf: Do not call smp_processor_id from preemptible
  coresight: tmc-etr: Do not call smp_processor_id() from preemptible
  docs: misc-devices: convert files without extension to ReST
  fpga: dfl: fme: align PR buffer size per PR datawidth
  fpga: dfl: fme: remove copy_to_user() in ioctl for PR
  fpga: dfl-fme-mgr: fix FME_PR_INTFC_ID register address.
  intel_th: msu: Start read iterator from a non-empty window
  intel_th: msu: Split sgt array and pointer in multiwindow mode
  intel_th: msu: Support multipage blocks
  intel_th: pci: Add Ice Lake NNPI support
  intel_th: msu: Fix single mode with disabled IOMMU
  ...
parents 4832a4da 2f4281f4

Documentation/ABI/testing/debugfs-driver-habanalabs

+15 −3
Original line number Diff line number Diff line
@@ -3,7 +3,10 @@ Date: Jan 2019 
KernelVersion:  5.1

Contact:        oded.gabbay@gmail.com

Description:    Sets the device address to be used for read or write through

                PCI bar. The acceptable value is a string that starts with "0x"

                PCI bar, or the device VA of a host mapped memory to be read or

                written directly from the host. The latter option is allowed

                only when the IOMMU is disabled.

                The acceptable value is a string that starts with "0x"



What:           /sys/kernel/debug/habanalabs/hl<n>/command_buffers

Date:           Jan 2019
@@ -33,10 +36,12 @@ Contact: oded.gabbay@gmail.com 
Description:    Allows the root user to read or write directly through the

                device's PCI bar. Writing to this file generates a write

                transaction while reading from the file generates a read

                transcation. This custom interface is needed (instead of using

                transaction. This custom interface is needed (instead of using

                the generic Linux user-space PCI mapping) because the DDR bar

                is very small compared to the DDR memory and only the driver can

                move the bar before and after the transaction

                move the bar before and after the transaction.

                If the IOMMU is disabled, it also allows the root user to read

                or write from the host a device VA of a host mapped memory



What:           /sys/kernel/debug/habanalabs/hl<n>/device

Date:           Jan 2019
@@ -46,6 +51,13 @@ Description: Enables the root user to set the device to specific state. 
                Valid values are "disable", "enable", "suspend", "resume".

                User can read this property to see the valid values



What:           /sys/kernel/debug/habanalabs/hl<n>/engines

Date:           Jul 2019

KernelVersion:  5.3

Contact:        oded.gabbay@gmail.com

Description:    Displays the status registers values of the device engines and

                their derived idle status



What:           /sys/kernel/debug/habanalabs/hl<n>/i2c_addr

Date:           Jan 2019

KernelVersion:  5.1

Documentation/ABI/testing/sysfs-driver-habanalabs

+24 −18
Original line number Diff line number Diff line
@@ -62,18 +62,20 @@ What: /sys/class/habanalabs/hl<n>/ic_clk 
Date:           Jan 2019

KernelVersion:  5.1

Contact:        oded.gabbay@gmail.com

Description:    Allows the user to set the maximum clock frequency of the

                Interconnect fabric. Writes to this parameter affect the device

                only when the power management profile is set to "manual" mode.

                The device IC clock might be set to lower value then the

Description:    Allows the user to set the maximum clock frequency, in Hz, of

                the Interconnect fabric. Writes to this parameter affect the

                device only when the power management profile is set to "manual"

                mode. The device IC clock might be set to lower value than the

                maximum. The user should read the ic_clk_curr to see the actual

                frequency value of the IC

                frequency value of the IC. This property is valid only for the

                Goya ASIC family



What:           /sys/class/habanalabs/hl<n>/ic_clk_curr

Date:           Jan 2019

KernelVersion:  5.1

Contact:        oded.gabbay@gmail.com

Description:    Displays the current clock frequency of the Interconnect fabric

Description:    Displays the current clock frequency, in Hz, of the Interconnect

                fabric. This property is valid only for the Goya ASIC family



What:           /sys/class/habanalabs/hl<n>/infineon_ver

Date:           Jan 2019
@@ -92,18 +94,20 @@ What: /sys/class/habanalabs/hl<n>/mme_clk 
Date:           Jan 2019

KernelVersion:  5.1

Contact:        oded.gabbay@gmail.com

Description:    Allows the user to set the maximum clock frequency of the

                MME compute engine. Writes to this parameter affect the device

                only when the power management profile is set to "manual" mode.

                The device MME clock might be set to lower value then the

Description:    Allows the user to set the maximum clock frequency, in Hz, of

                the MME compute engine. Writes to this parameter affect the

                device only when the power management profile is set to "manual"

                mode. The device MME clock might be set to lower value than the

                maximum. The user should read the mme_clk_curr to see the actual

                frequency value of the MME

                frequency value of the MME. This property is valid only for the

                Goya ASIC family



What:           /sys/class/habanalabs/hl<n>/mme_clk_curr

Date:           Jan 2019

KernelVersion:  5.1

Contact:        oded.gabbay@gmail.com

Description:    Displays the current clock frequency of the MME compute engine

Description:    Displays the current clock frequency, in Hz, of the MME compute

                engine. This property is valid only for the Goya ASIC family



What:           /sys/class/habanalabs/hl<n>/pci_addr

Date:           Jan 2019
@@ -163,18 +167,20 @@ What: /sys/class/habanalabs/hl<n>/tpc_clk 
Date:           Jan 2019

KernelVersion:  5.1

Contact:        oded.gabbay@gmail.com

Description:    Allows the user to set the maximum clock frequency of the

                TPC compute engines. Writes to this parameter affect the device

                only when the power management profile is set to "manual" mode.

                The device TPC clock might be set to lower value then the

Description:    Allows the user to set the maximum clock frequency, in Hz, of

                the TPC compute engines. Writes to this parameter affect the

                device only when the power management profile is set to "manual"

                mode. The device TPC clock might be set to lower value than the

                maximum. The user should read the tpc_clk_curr to see the actual

                frequency value of the TPC

                frequency value of the TPC. This property is valid only for

                Goya ASIC family



What:           /sys/class/habanalabs/hl<n>/tpc_clk_curr

Date:           Jan 2019

KernelVersion:  5.1

Contact:        oded.gabbay@gmail.com

Description:    Displays the current clock frequency of the TPC compute engines

Description:    Displays the current clock frequency, in Hz, of the TPC compute

                engines. This property is valid only for the Goya ASIC family



What:           /sys/class/habanalabs/hl<n>/uboot_ver

Date:           Jan 2019

Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt

+2 −2
Original line number Diff line number Diff line
@@ -26,8 +26,8 @@ Required properties: 
		processor core is clocked by the internal CPU clock, so it

		is enabled with CPU clock by default.



- cpu : the CPU phandle the debug module is affined to. When omitted

	the module is considered to belong to CPU0.

- cpu : the CPU phandle the debug module is affined to. Do not assume it

        to default to CPU0 if omitted.



Optional properties:

Documentation/devicetree/bindings/arm/coresight.txt

+5 −3
Original line number Diff line number Diff line
@@ -59,6 +59,11 @@ its hardware characteristcs. 


	* port or ports: see "Graph bindings for Coresight" below.



* Additional required property for Embedded Trace Macrocell (version 3.x and

  version 4.x):

	* cpu: the cpu phandle this ETM/PTM is affined to. Do not

	  assume it to default to CPU0 if omitted.



* Additional required properties for System Trace Macrocells (STM):

	* reg: along with the physical base address and length of the register

	  set as described above, another entry is required to describe the
@@ -87,9 +92,6 @@ its hardware characteristcs. 
	* arm,cp14: must be present if the system accesses ETM/PTM management

	  registers via co-processor 14.



	* cpu: the cpu phandle this ETM/PTM is affined to. When omitted the

	  source is considered to belong to CPU0.



* Optional property for TMC:



	* arm,buffer-size: size of contiguous buffer space for TMC ETR

Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt

+22 −0
Original line number Diff line number Diff line
@@ -133,6 +133,18 @@ RTC bindings based on SCU Message Protocol 
Required properties:

- compatible: should be "fsl,imx8qxp-sc-rtc";



OCOTP bindings based on SCU Message Protocol

------------------------------------------------------------

Required properties:

- compatible:		Should be "fsl,imx8qxp-scu-ocotp"

- #address-cells:	Must be 1. Contains byte index

- #size-cells:		Must be 1. Contains byte length



Optional Child nodes:



- Data cells of ocotp:

  Detailed bindings are described in bindings/nvmem/nvmem.txt



Example (imx8qxp):

-------------

aliases {
@@ -177,6 +189,16 @@ firmware { 
			...

		};



		ocotp: imx8qx-ocotp {

			compatible = "fsl,imx8qxp-scu-ocotp";

			#address-cells = <1>;

			#size-cells = <1>;



			fec_mac0: mac@2c4 {

				reg = <0x2c4 8>;

			};

		};



		pd: imx8qx-pd {

			compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";

			#power-domain-cells = <1>;

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