Commit 97e02140 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel 

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
  drm/i915: fix page flip finish vs. prepare on plane B
  drm/i915: change default panel fitting mode to preserve aspect ratio
  drm/i915: fix uninitialized variable warning in i915_setup_compression()
  drm/i915: take struct_mutex in i915_dma_cleanup()
  drm/i915: Fix CRT hotplug regression in 2.6.35-rc1
  i915: fix ironlake edp panel setup (v4)
  drm/i915: don't access FW_BLC_SELF on 965G
  drm/i915: Account for space on the ring buffer consumed whilst wrapping.
  drm/i915: gen3 page flipping fixes
  drm/i915: don't queue flips during a flip pending event
  drm/i915: Fix incorrect intel_ring_begin size in BSD ringbuffer.
  drm/i915: Turn on 945 self-refresh only if single CRTC is active
  drm/i915/gen4: Fix interrupt setup ordering
  drm/i915: Use RSEN instead of HTPLG for tfp410 monitor detection.
  drm/i915: Move non-phys cursors into the GTT
  Revert "drm/i915: Don't enable pipe/plane/VCO early (wait for DPMS on)."

(Included the "fix page flip finish vs.  prepare on plane B" patch from
Jesse on top of the pull request from Eric.   -- Linus)
parents 82645698 70565d00

drivers/gpu/drm/i915/dvo_tfp410.c

+1 −1
Original line number Diff line number Diff line
@@ -208,7 +208,7 @@ static enum drm_connector_status tfp410_detect(struct intel_dvo_device *dvo) 
	uint8_t ctl2;



	if (tfp410_readb(dvo, TFP410_CTL_2, &ctl2)) {

		if (ctl2 & TFP410_CTL_2_HTPLG)

		if (ctl2 & TFP410_CTL_2_RSEN)

			ret = connector_status_connected;

		else

			ret = connector_status_disconnected;

drivers/gpu/drm/i915/i915_debugfs.c

+1 −1
Original line number Diff line number Diff line
@@ -620,7 +620,7 @@ static int i915_sr_status(struct seq_file *m, void *unused) 
	drm_i915_private_t *dev_priv = dev->dev_private;

	bool sr_enabled = false;



	if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev))

	if (IS_I965GM(dev) || IS_I945G(dev) || IS_I945GM(dev))

		sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;

	else if (IS_I915GM(dev))

		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;

drivers/gpu/drm/i915/i915_dma.c

+7 −1
Original line number Diff line number Diff line
@@ -128,9 +128,11 @@ static int i915_dma_cleanup(struct drm_device * dev) 
	if (dev->irq_enabled)

		drm_irq_uninstall(dev);



	mutex_lock(&dev->struct_mutex);

	intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);

	if (HAS_BSD(dev))

		intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);

	mutex_unlock(&dev->struct_mutex);



	/* Clear the HWS virtual address at teardown */

	if (I915_NEED_GFX_HWS(dev))
@@ -1229,7 +1231,7 @@ static void i915_warn_stolen(struct drm_device *dev) 
static void i915_setup_compression(struct drm_device *dev, int size)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_mm_node *compressed_fb, *compressed_llb;

	struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);

	unsigned long cfb_base;

	unsigned long ll_base = 0;
@@ -1410,6 +1412,10 @@ static int i915_load_modeset_init(struct drm_device *dev, 
	if (ret)

		goto cleanup_vga_client;



	/* IIR "flip pending" bit means done if this bit is set */

	if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))

		dev_priv->flip_pending_is_done = true;



	intel_modeset_init(dev);



	ret = drm_irq_install(dev);

drivers/gpu/drm/i915/i915_drv.h

+2 −1
Original line number Diff line number Diff line
@@ -596,6 +596,7 @@ typedef struct drm_i915_private { 
	struct drm_crtc *plane_to_crtc_mapping[2];

	struct drm_crtc *pipe_to_crtc_mapping[2];

	wait_queue_head_t pending_flip_queue;

	bool flip_pending_is_done;



	/* Reclocking support */

	bool render_reclock_avail;
@@ -1076,7 +1077,7 @@ extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); 
	drm_i915_private_t *dev_priv = dev->dev_private;                \

	if (I915_VERBOSE)						\

		DRM_DEBUG("   BEGIN_LP_RING %x\n", (int)(n));		\

	intel_ring_begin(dev, &dev_priv->render_ring, 4*(n));		\

	intel_ring_begin(dev, &dev_priv->render_ring, (n));		\

} while (0)

drivers/gpu/drm/i915/i915_irq.c

+45 −31
Original line number Diff line number Diff line
@@ -940,21 +940,29 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) 
		if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))

			DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);



		if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)

		if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {

			intel_prepare_page_flip(dev, 0);

			if (dev_priv->flip_pending_is_done)

				intel_finish_page_flip_plane(dev, 0);

		}



		if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)

		if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {

			intel_prepare_page_flip(dev, 1);

			if (dev_priv->flip_pending_is_done)

				intel_finish_page_flip_plane(dev, 1);

		}



		if (pipea_stats & vblank_status) {

			vblank++;

			drm_handle_vblank(dev, 0);

			if (!dev_priv->flip_pending_is_done)

				intel_finish_page_flip(dev, 0);

		}



		if (pipeb_stats & vblank_status) {

			vblank++;

			drm_handle_vblank(dev, 1);

			if (!dev_priv->flip_pending_is_done)

				intel_finish_page_flip(dev, 1);

		}
@@ -1387,29 +1395,10 @@ int i915_driver_irq_postinstall(struct drm_device *dev) 
	dev_priv->pipestat[1] = 0;



	if (I915_HAS_HOTPLUG(dev)) {

		u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);



		/* Note HDMI and DP share bits */

		if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)

			hotplug_en |= HDMIB_HOTPLUG_INT_EN;

		if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)

			hotplug_en |= HDMIC_HOTPLUG_INT_EN;

		if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)

			hotplug_en |= HDMID_HOTPLUG_INT_EN;

		if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)

			hotplug_en |= SDVOC_HOTPLUG_INT_EN;

		if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)

			hotplug_en |= SDVOB_HOTPLUG_INT_EN;

		if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)

			hotplug_en |= CRT_HOTPLUG_INT_EN;

		/* Ignore TV since it's buggy */



		I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);



		/* Enable in IER... */

		enable_mask |= I915_DISPLAY_PORT_INTERRUPT;

		/* and unmask in IMR */

		i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);

		dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;

	}



	/*
@@ -1427,16 +1416,41 @@ int i915_driver_irq_postinstall(struct drm_device *dev) 
	}

	I915_WRITE(EMR, error_mask);



	/* Disable pipe interrupt enables, clear pending pipe status */

	I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);

	I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);

	/* Clear pending interrupt status */

	I915_WRITE(IIR, I915_READ(IIR));



	I915_WRITE(IER, enable_mask);

	I915_WRITE(IMR, dev_priv->irq_mask_reg);

	I915_WRITE(IER, enable_mask);

	(void) I915_READ(IER);



	if (I915_HAS_HOTPLUG(dev)) {

		u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);



		/* Note HDMI and DP share bits */

		if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)

			hotplug_en |= HDMIB_HOTPLUG_INT_EN;

		if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)

			hotplug_en |= HDMIC_HOTPLUG_INT_EN;

		if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)

			hotplug_en |= HDMID_HOTPLUG_INT_EN;

		if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)

			hotplug_en |= SDVOC_HOTPLUG_INT_EN;

		if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)

			hotplug_en |= SDVOB_HOTPLUG_INT_EN;

		if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {

			hotplug_en |= CRT_HOTPLUG_INT_EN;



			/* Programming the CRT detection parameters tends

			   to generate a spurious hotplug event about three

			   seconds later.  So just do it once.

			*/

			if (IS_G4X(dev))

				hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;

			hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;

		}



		/* Ignore TV since it's buggy */



		I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);

	}



	opregion_enable_asle(dev);



	return 0;

CRA Git | Maintained and supported by SUSTech CRA and CCSE