Commit 97df424f authored by Harry Wentland's avatar Harry Wentland Committed by Alex Deucher
Browse files

drm/amd/display: Drop DCN1_01 guards 



[WHY]
These were only needed for bringup. They're not needed anymore.

Signed-off-by: default avatarHarry Wentland <harry.wentland@amd.com>
Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a7669aff

drivers/gpu/drm/amd/display/Kconfig

+0 −6
Original line number Diff line number Diff line
@@ -5,7 +5,6 @@ config DRM_AMD_DC 
	bool "AMD DC - Enable new display engine"

	default y

	select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)

	select DRM_AMD_DC_DCN1_01 if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)

	help

	  Choose this option if you want to use the new display engine

	  support for AMDGPU. This adds required support for Vega and
@@ -16,11 +15,6 @@ config DRM_AMD_DC_DCN1_0 
	help

	  RV family support for display engine



config DRM_AMD_DC_DCN1_01

	def_bool n

	help

	  RV2 family for display engine



config DEBUG_KERNEL_DC

	bool "Enable kgdb break in DC"

	depends on DRM_AMD_DC

drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c

+0 −5
Original line number Diff line number Diff line
@@ -57,11 +57,6 @@ bool dal_bios_parser_init_cmd_tbl_helper2( 
		return true;

#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

	case DCN_VERSION_1_0:

		*h = dal_cmd_tbl_helper_dce112_get_table2();

		return true;

#endif



#if defined(CONFIG_DRM_AMD_DC_DCN1_01)

	case DCN_VERSION_1_01:

		*h = dal_cmd_tbl_helper_dce112_get_table2();

		return true;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+0 −4
Original line number Diff line number Diff line
@@ -93,10 +93,8 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) 
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

	case FAMILY_RV:

		dc_version = DCN_VERSION_1_0;

#if defined(CONFIG_DRM_AMD_DC_DCN1_01)

		if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))

			dc_version = DCN_VERSION_1_01;

#endif

		break;

#endif

	default:
@@ -147,9 +145,7 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, 


#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

	case DCN_VERSION_1_0:

#if defined(CONFIG_DRM_AMD_DC_DCN1_01)

	case DCN_VERSION_1_01:

#endif

		res_pool = dcn10_create_resource_pool(init_data, dc);

		break;

#endif

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c

+0 −2
Original line number Diff line number Diff line
@@ -927,9 +927,7 @@ void hubbub1_construct(struct hubbub *hubbub, 
	hubbub1->masks = hubbub_mask;



	hubbub1->debug_test_index_pstate = 0x7;

#if defined(CONFIG_DRM_AMD_DC_DCN1_01)

	if (ctx->dce_version == DCN_VERSION_1_01)

		hubbub1->debug_test_index_pstate = 0xB;

#endif

}

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

+0 −19
Original line number Diff line number Diff line
@@ -152,9 +152,7 @@ enum dcn10_clk_src_array_id { 
	DCN10_CLK_SRC_PLL2,

	DCN10_CLK_SRC_PLL3,

	DCN10_CLK_SRC_TOTAL,

#if defined(CONFIG_DRM_AMD_DC_DCN1_01)

	DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3

#endif

};



/* begin *********************
@@ -522,7 +520,6 @@ static const struct resource_caps res_cap = { 
		.num_ddc = 4,

};



#if defined(CONFIG_DRM_AMD_DC_DCN1_01)

static const struct resource_caps rv2_res_cap = {

		.num_timing_generator = 3,

		.num_opp = 3,
@@ -532,7 +529,6 @@ static const struct resource_caps rv2_res_cap = { 
		.num_pll = 3,

		.num_ddc = 3,

};

#endif



static const struct dc_plane_cap plane_cap = {

	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
@@ -1270,11 +1266,9 @@ static bool construct( 


	ctx->dc_bios->regs = &bios_regs;



#if defined(CONFIG_DRM_AMD_DC_DCN1_01)

	if (ctx->dce_version == DCN_VERSION_1_01)

		pool->base.res_cap = &rv2_res_cap;

	else

#endif

		pool->base.res_cap = &res_cap;

	pool->base.funcs = &dcn10_res_pool_funcs;
@@ -1291,10 +1285,8 @@ static bool construct( 
	/* max pipe num for ASIC before check pipe fuses */

	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;



#if defined(CONFIG_DRM_AMD_DC_DCN1_01)

	if (dc->ctx->dce_version == DCN_VERSION_1_01)

		pool->base.pipe_count = 3;

#endif

	dc->caps.max_video_width = 3840;

	dc->caps.max_downscale_ratio = 200;

	dc->caps.i2c_speed_in_khz = 100;
@@ -1327,26 +1319,17 @@ static bool construct( 
				CLOCK_SOURCE_COMBO_PHY_PLL2,

				&clk_src_regs[2], false);



#ifdef CONFIG_DRM_AMD_DC_DCN1_01

	if (dc->ctx->dce_version == DCN_VERSION_1_0) {

		pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =

				dcn10_clock_source_create(ctx, ctx->dc_bios,

					CLOCK_SOURCE_COMBO_PHY_PLL3,

					&clk_src_regs[3], false);

	}

#else

	pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =

			dcn10_clock_source_create(ctx, ctx->dc_bios,

				CLOCK_SOURCE_COMBO_PHY_PLL3,

				&clk_src_regs[3], false);

#endif



	pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;



#if defined(CONFIG_DRM_AMD_DC_DCN1_01)

	if (dc->ctx->dce_version == DCN_VERSION_1_01)

		pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;

#endif



	pool->base.dp_clock_source =

			dcn10_clock_source_create(ctx, ctx->dc_bios,
@@ -1386,7 +1369,6 @@ static bool construct( 
	memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));

	memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));



#if defined(CONFIG_DRM_AMD_DC_DCN1_01)

	if (dc->ctx->dce_version == DCN_VERSION_1_01) {

		struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;

		struct dcn_ip_params *dcn_ip = dc->dcn_ip;
@@ -1397,7 +1379,6 @@ static bool construct( 
		dcn_soc->dram_clock_change_latency = 23;

		dcn_ip->max_num_dpp = 3;

	}

#endif

	if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {

		dc->dcn_soc->urgent_latency = 3;

		dc->debug.disable_dmcu = true;

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